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arXiv · 1806.02173

Study of Full Parallel RS(31,27) Encoder for a 3.2 Gbps Serial Transmitter in 0.18 um CMOS Technology

Guangyu Zhang·Quan Sun·Tiankuan Liu·Datao Gong·Dongxu Yang·Yi Feng·Jian Wang
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Abstract

This work presents the design of an RS(31,27) Reed Solomon encoder for a 3.2 Gbps serial transmitter in 0.18 um CMOS technology. The proposed encoder is designed with a novel full parallel structure optimized for high speed and high stability. One data frame contains 2 interleaved RS(31,27) codes and thus it can correct at most 20 bits of consecutive errors. A corresponding decoder is implemented on Xilinx Kintex-7 FPGA.

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Guangyu Zhang, Quan Sun, Tiankuan Liu, Datao Gong, Dongxu Yang, Yi Feng, Jian Wang. 2018-06-03. Study of Full Parallel RS(31,27) Encoder for a 3.2 Gbps Serial Transmitter in 0.18 um CMOS Technology. https://doi.org/10.1088/1748-0221/14/02/p02028

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