Design of CMOS-memristor Circuits for LSTM architecture

Kamilya Smagulova; Kazybek Adam; Olga Krestinskaya; Alex Pappachen James

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arXiv · 1806.02366

Design of CMOS-memristor Circuits for LSTM architecture

Kamilya Smagulova·Kazybek Adam·Olga Krestinskaya·Alex Pappachen James

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Abstract

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

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Kamilya Smagulova, Kazybek Adam, Olga Krestinskaya, Alex Pappachen James. 2018-06-06. Design of CMOS-memristor Circuits for LSTM architecture. https://arxiv.org/abs/1806.02366

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