arXiv subjects

Alex Pappachen James

Publications and source records attributed to Alex Pappachen James.

At least 19 recordsLinked to original sources

arXiv2020

AM-DCGAN: Analog Memristive Hardware Accelerator for Deep Convolutional Generative Adversarial Networks

Generative Adversarial Network (GAN) is a well known computationally complex algorithm requiring signficiant computational resources in software implementations including large amount of data to be trained. This makes its implementation in edge devices with conventional microprocessor hardware a slow and difficult task. In this paper, we propose to accelerate the computationally intensive GAN using memristive neural networks in analog domain. We present a fully analog hardware design of Deep Convolutional GAN (DCGAN) based on CMOS-memristive convolutional and deconvolutional networks simulated using 180nm CMOS technology.

cs.ET↗

arXiv2019

Variability analysis of Memristor-based Sigmoid Function

Activation functions are widely used in neural networks to decide the activation value of the neural unit based upon linear combinations of the weighted inputs. The effective implementation of activation function is highly important, as they help to represent non-linear complex functional mappings between inputs and outputs of the neural network. One of the non-linear approaches is to use a sigmoid function. Therefore, there is a growing need in enhancing the performance of sigmoid circuits. In this paper, the main objective is to modify existing current mirror based sigmoid model by replacing CMOS transistors with memristor devices. This model was tested varying different circuit parameters, transistor size and temperature. The the area, power and noise in the modified CMOS-memristive sigmoid circuit are shown. The application of memristors in the sigmoid circuit results in higher component density in an on-chip area, allowing a reduction of power and area by 7$\%$. The proposed sigmoid circuit was simulated in SPICE using 180nm TSMC CMOS technology.

cs.ET↗

arXiv2019

Analysis of Multilayer Perceptron with Rectifier Linear Unit Activation Function

The implementation of analog neural network and online analog learning circuits based on memristive crossbar has been intensively explored in recent years. The implementation of various activation functions is important, especially for deep leaning neural networks. There are several implementations of sigmoid and tangent activation function, while the implementation of the neural networks with linear activation functions is an open problem. Therefore, this paper introduces a multilayer perceptron design with linear activation function. The temperature and noise analysis was performed. The perceptron showed a good performance and strong durability to temperature changes.

cs.ET↗

arXiv2019

CMOS-Memristive Analog Multiplier Design

This paper proposes four quadrant analog multiplier using CMOS-memristor circuit. Currently, there are plenty of analog multipliers using resistors and CMOS transistors. They can attain perfect multiplication but have several disadvantages such as lower processing speed, higher power consumption and larger chip areas. Memristor based circuits are introduced to resolve the mentioned drawbacks. In this paper current mode four quadrant multiplier based on squaring circuits is taken as a framework, and CMOS transistors are replaced with memristors. The circuit design is simulated with SPICE, and variability analysis and performance variation with temperature is performed. The proposed circuit allows faster processing with retained data while dissipating less power retaining the multiplication characteristics.

cs.ET↗

arXiv2019

An overview of memristive cryptography

Smaller, smarter and faster edge devices in the Internet of things era demands secure data analysis and transmission under resource constraints of hardware architecture. Lightweight cryptography on edge hardware is an emerging topic that is essential to ensure data security in near-sensor computing systems such as mobiles, drones, smart cameras, and wearables. In this article, the current state of memristive cryptography is placed in the context of lightweight hardware cryptography. The paper provides a brief overview of the traditional hardware lightweight cryptography and cryptanalysis approaches. The contrast for memristive cryptography with respect to traditional approaches is evident through this article, and need to develop a more concrete approach to developing memristive cryptanalysis to test memristive cryptographic approaches is highlighted.

cs.ET↗

arXiv2018

Neuro-memristive Circuits for Edge Computing: A review

The volume, veracity, variability, and velocity of data produced from the ever-increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing.

cs.ET↗

arXiv2018

Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices

The memristor can be used as non volatile memory (NVM) and for emulating neuron behavior. It has the ability to switch between low resistance $R_{on}$ and high resistance values $R_{off}$, and exhibit the synaptic dynamic behaviour such as potentiation and depression. This paper presents a study on potentiation and depression of memristors in Quad Flat Pack. A comparison is drawn between the memristors with and without the impact of parasitics of packaging, using measured data and equivalent circuit models. The parameters in memristor and packaging models for the SPICE simulations were determined using measured data to reflect the memristor parasitics in Quad Flat Packs.

cs.ET↗

arXiv2018

Wafer Quality Inspection using Memristive LSTM, ANN, DNN and HTM

The automated wafer inspection and quality control is a complex and time-consuming task, which can speed up using neuromorphic memristive architectures, as a separate inspection device or integrating directly into sensors. This paper presents the performance analysis and comparison of different neuromorphic architectures for patterned wafer quality inspection and classification. The application of non-volatile memristive devices in these architectures ensures low power consumption, small on-chip area scalability. We demonstrate that Long-Short Term Memory (LSTM) outperforms other architectures for the same number of training iterations, and has relatively low on-chip area and power consumption.

cs.ET↗

arXiv2018

Memristive LSTM network hardware architecture for time-series predictive modeling problem

Analysis of time-series data allows to identify long-term trends and make predictions that can help to improve our lives. With the rapid development of artificial neural networks, long short-term memory (LSTM) recurrent neural network (RNN) configuration is found to be capable in dealing with time-series forecasting problems where data points are time-dependent and possess seasonality trends. Gated structure of LSTM cell and flexibility in network topology (one-to-many, many-to-one, etc.) allows to model systems with multiple input variables and control several parameters such as the size of the look-back window to make a prediction and number of time steps to be predicted. These make LSTM attractive tool over conventional methods such as autoregression models, the simple average, moving average, naive approach, ARIMA, Holt's linear trend method, Holt's Winter seasonal method, and others. In this paper, we propose a hardware implementation of LSTM network architecture for time-series forecasting problem. All simulations were performed using TSMC 0.18um CMOS technology and HP memristor model.

cs.ET↗

arXiv2018

Programmable Memristive Threshold Logic Gate Array

This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC $180nm$ CMOS technology. The on-chip area and power dissipation of the simulated $3\times 4$ TLG array is $1463 μm^2$ and $425 μW$, respectively.

cs.ET↗

arXiv2018

Learning in Memristive Neural Network Architectures using Analog Backpropagation Circuits

The on-chip implementation of learning algorithms would speed-up the training of neural networks in crossbar arrays. The circuit level design and implementation of backpropagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we proposed the analog backpropagation learning circuits for various memristive learning architectures, such as Deep Neural Network (DNN), Binary Neural Network (BNN), Multiple Neural Network (MNN), Hierarchical Temporal Memory (HTM) and Long-Short Term Memory (LSTM). The circuit design and verification is done using TSMC 180nm CMOS process models, and TiO2 based memristor models. The application level validations of the system are done using XOR problem, MNIST character and Yale face image databases

cs.ET↗

arXiv2018

Real-time Analog Pixel-to-pixel Dynamic Frame Differencing with Memristive Sensing Circuits

In this paper, we propose an analog pixel differencing circuit for differentiating pixels between frames directly from CMOS pixels. The analog information processing at sensor is a topic of growing appeal to develop edge AI devices. The proposed circuit is integrated into a pixel-parallel and pixel-column architectures. The proposed system is design using TSMC $180nm$ CMOS technology. The power dissipation of the proposed circuit is $96.64mW$, and on-chip ares is $531.66 μm^2$. The architectures are tested for moving object detection application.

cs.ET↗

arXiv2018

Memristor-based Synaptic Sampling Machines

Synaptic Sampling Machine (SSM) is a type of neural network model that considers biological unreliability of the synapses. We propose the circuit design of the SSM neural network which is realized through the memristive-CMOS crossbar structure with the synaptic sampling cell (SSC) being used as a basic stochastic unit. The increase in the edge computing devices in the Internet of things era, drives the need for hardware acceleration for data processing and computing. The computational considerations of the processing speed and possibility for the real-time realization pushes the synaptic sampling algorithm that demonstrated promising results on software for hardware implementation.

cs.ET↗

arXiv2018

Approximate Probabilistic Neural Networks with Gated Threshold Logic

Probabilistic Neural Network (PNN) is a feed-forward artificial neural network developed for solving classification problems. This paper proposes a hardware implementation of an approximated PNN (APNN) algorithm in which the conventional exponential function of the PNN is replaced with gated threshold logic. The weights of the PNN are approximated using a memristive crossbar architecture. In particular, the proposed algorithm performs normalization of the training weights, and quantization into 16 levels which significantly reduces the complexity of the circuit.

cs.ET↗

arXiv2018

Binary Weighted Memristive Analog Deep Neural Network for Near-Sensor Edge Processing

The memristive crossbar aims to implement analog weighted neural network, however, the realistic implementation of such crossbar arrays is not possible due to limited switching states of memristive devices. In this work, we propose the design of an analog deep neural network with binary weight update through backpropagation algorithm using binary state memristive devices. We show that such networks can be successfully used for image processing task and has the advantage of lower power consumption and small on-chip area in comparison with digital counterparts. The proposed network was benchmarked for MNIST handwritten digits recognition achieving an accuracy of approximately 90%.

cs.ET↗

arXiv2018

Design of CMOS-memristor Circuits for LSTM architecture

Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.

cs.ET↗

arXiv2018

Effects of Memristors on Fully Differential Transimpedance Amplifier Performance

The progress of the Internet of Things(IoT) technologies and applications requires the efficient low power circuits and architectures to maintain and improve the performance of the increasingly growing data processing systems. Memristive circuits and substitution of energy-consuming devices with memristors is a promising solution to reduce on-chip area and power dissipation of the architectures. In this paper, we proposed a CMOS-memristive fully differential transimpedance amplifier and assess the impact of memristors on the amplifier performance. The fully differential amplifiers were simulated using 180nm CMOS technology and have 5.3-23MHz bandwidths and 2.3-5.7k$Ω$ transimpedance gains with a 1pF load. We compare the memristor based amplifier with conventional architecture. The gain, frequency response, linear range, power consumption, area, total harmonic distortion and performance variations with temperature are reported.

cs.ET↗

arXiv2018

Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator

The cryptographic security provided by various techniques of random number generator (RNG) construction is one of the developing researches areas today. Among various types of RNG, the true random bit generator (TRBG) can be considered as the most unpredictable and most secured because its randomness seed is generated from chaotic sources. This paper proposes a design of TRBG model based on double-scroll attractors circuits with GST memristor. After implementation and simulation of the chaotic circuit with GST memristor emulator, the chaotic behavior of the output voltage and inductor current were received. Moreover, their dependence on the input voltage revealed the close to double-scroll form. The randomness generated from the proposed circuit was tested by receiving Fast Fourier Transform (FFT) and Lyapunov exponents of the output voltage.

eess.SP↗