1/f Noise Reduction using In-Pixel Chopping in CMOS Image Sensor

Kapil Jainwal; Mukul Sarkar

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arXiv · 1807.11577

1/f Noise Reduction using In-Pixel Chopping in CMOS Image Sensor

Kapil Jainwal·Mukul Sarkar

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Abstract

In this paper, an in-pixel chopping technique to reduce the low-frequency or 1/f noise of the source follower (SF) transistor in an active pixel sensor (APS) is presented. The SF low-frequency noise is modulated at higher frequencies through chopping, implemented inside the pixel, and in later stage eliminated using low-pass filtering. To implement the chopping, the conventional 3T APS architecture is modified, with only one additional transistor of minimum size per pixel. Reduction in the noise also enhances the dynamic range (DR) of the image sensor. The test circuit is fabricated in UMC 0.18 um standard CMOS technology. The measured results show a reduction of 1/f noise by approximately 22 dB for 50 MHz chopping frequency.

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BibTeX RIS

Kapil Jainwal, Mukul Sarkar. 2018-07-27. 1/f Noise Reduction using In-Pixel Chopping in CMOS Image Sensor. https://arxiv.org/abs/1807.11577

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