SearcharxivSearch

arXiv · 1812.03862

Speed Based Optimal Power Control in Small Cell Networks

Abstract

Small cell networks promise good quality of service (QoS) even for cell edge users, however pose challenges to cater to the high-speed users. The major difficulty being that of frequent handovers and the corresponding handover losses, which significantly depend upon the speed of the user. It was shown previously that the optimal cell size increases with speed. Thus, in scenarios with diverse users (speeds spanning over large ranges), it would be inefficient to serve all users using common cell radius and it is practically infeasible to design different cell sizes for different speeds. Alternatively, we propose to allocate power to a user based on its speed, e.g., higher power virtually increases the cell size. We solve well known Hamiltonian Jacobi equations under certain assumptions to obtain a power law, optimal for load factor and busy probability, for any given average power constraint and cell size. The optimal power control turns out to be linear in speed. We build a system level simulator for small cell network, using elaborate Monte-Carlo simulations, and show that the performance of the system improves significantly with linear power law. The power law is tested even for the cases, for which the system does not satisfy the assumptions required by the theory. For example, the linear power law has significant improvement in comparison with the 'equal power' system, even in presence of time varying and random interference. We observe good improvement in almost all cases with improvements up to 89\% for certain configurations.

Explore related subjects

Keep this discovery

BibTeXRIS

Veeraruna Kavitha, Manu K. Gupta, Veronique Capdevielle, Rahul Kishor, Majed Haddad. 2018-12-10. Speed Based Optimal Power Control in Small Cell Networks. https://doi.org/10.1016/j.comcom.2019.04.009

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

PASCAL: A Phase-Aware Shared-Cache Model for Parallel Scans

In modern AI Accelerators and GPGPUs, many concurrent cores repeatedly access the same shared data. This pattern occurs in attention, where different query tiles share the same K/V block, GEMM, where every tile in a row reads the same panel, and many other operators. We name this pattern parallel scan. Due to a significant amount of data reuse in this pattern, the cache is expected to capture as much data reuse as possible and largely reduce requests sent to the main memory for both performance and energy consumption concerns. However, in reality, because of the intrinsic asynchrony of multi-cores, the actual cache miss rate and DRAM traffic can be much higher compared to ideal cases. In this paper, we propose PASCAL, a shared-cache model for parallel scans. It is aware of the dynamic feature of progress divergence across multi-cores, correlate the divergence with the combination of different factors such as occupancy, and predicts the cache miss rate before execution. Because prediction needs no target trace, timing, or counters, PASCAL supports design-space exploration at scales where cycle-accurate simulation is impractical, and its policy-independent bound states how much traffic no replacement policy can avoid. A MAPE of 13.84% is achieved in a 60-configuration dataset with various software pipeline depths, occupancies, and memory access data paths on an NVIDIA GB10 GPU, against 44.79% for physical-wave TileSight and 54.16% for exact symbolic SDCM.

cs.PF

Mathematical Modeling of a Cognitive Continuum Digital Shadow for Large-Scale, Cross-Facility Workflows

We present the mathematical foundations of a \emph{Cognitive Continuum Digital Shadow} (CCDS), a decision-support layer between users and the cross-facility infrastructure---instruments, networks, data stores and compute centers---of exascale and post-exascale scientific workflows. The CCDS couples a state-space representation of the continuum with multistage stochastic programming, so that deployment scenarios can be explored and optimized \emph{before} jobs are launched. This allows operators and users to quantify the cost, makespan and energy trade-offs of a workflow under uncertain resource availability, and hedge their decisions accordingly. We formulate the underlying optimization as a multimode, resource-constrained, stochastic supply-chain network design problem and demonstrate it on a realistic genomics workflow scheduled across heterogeneous HPC and data-center resources. This is the first of three papers; the second treats the underlying software architecture and the third reports large-scale use-cases.

cs.PF

RGB Input Pipelines: Throughput, GPU Memory, and Transformation Coverage

An image-augmentation pipeline must deliver a complete batch before a model can use it. We compare seven input paths from five libraries, starting with RGB JPEG files and ending with a synchronized CUDA float16 batch. We manually matched transformation recipes and parameters across libraries to make the workloads as comparable as possible. The experiment uses 57 selected recipes, a batch size of 256, and one NVIDIA L4 machine. Throughput and peak process GPU memory are recorded together in 759 measurements. On the 11 recipes shared by all paths, DALI and AlbumentationsX have median throughputs of 5,029 and 4,679 images/s, with median peak GPU memory of 2,086 and 1,852 MiB. Broader pairwise comparisons favor AlbumentationsX on 26/26 TorchVision recipes, 50/51 Kornia recipes, and 25/26 Pillow recipes. DALI is faster than AlbumentationsX on all 22 shared recipes, with a median throughput ratio of 1.18x. A separate census reports coverage of the 118 entries in a selected AlbumentationsX RGB catalog. The study measures input preparation at fixed settings; it does not measure model training, numerical equivalence, or the best attainable configuration of each library. Benchmark code: https://github.com/albumentations-team/benchmark.

cs.PF