Using Floating Gate Memory to Train Ideal Accuracy Neural Networks

Sapan Agarwal; Diana Garland; John Niroula; Robin B; Jacobs-Gedrim; Alex Hsia; Michael S. Van Heukelom; Elliot Fuller; Bruce Draper; Matthew J. Marinella

arXiv · 1901.10570

Using Floating Gate Memory to Train Ideal Accuracy Neural Networks

Sapan Agarwal·Diana Garland·John Niroula·Robin B·Jacobs-Gedrim·Alex Hsia·Michael S. Van Heukelom·Elliot Fuller·Bruce Draper·Matthew J. Marinella

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Abstract

Floating gate SONOS (Silicon-Oxygen-Nitrogen-Oxygen-Silicon) transistors can be used to train neural networks to ideal accuracies that match those of floating point digital weights on the MNIST dataset when using multiple devices to represent a weight or within 1% of ideal accuracy when using a single device. This is enabled by operating devices in the subthreshold regime, where they exhibit symmetric write nonlinearities. A neural training accelerator core based on SONOS with a single device per weight would increase energy efficiency by 120X, operate 2.1X faster and require 5X lower area than an optimized SRAM based ASIC.

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Sapan Agarwal, Diana Garland, John Niroula, Robin B, Jacobs-Gedrim, Alex Hsia, Michael S. Van Heukelom, Elliot Fuller, Bruce Draper, Matthew J. Marinella. 2019-01-29. Using Floating Gate Memory to Train Ideal Accuracy Neural Networks. https://arxiv.org/abs/1901.10570

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