arXiv subjects

John Niroula

Publications and source records attributed to John Niroula.

4 recordsLinked to original sources

arXiv2026

High-temperature operation of III-nitride high-electron-mobility transistors

High-electron-mobility transistors (HEMTs) made with III-nitride materials are of potential use in high-temperature electronic applications including power electronics, communications, aerospace and space exploration. However, the demands of such applications make it essential to understand the thermal limits and performance evolution of III-nitride HEMTs. Here, we analyze the high-temperature operation of III-nitride HEMTs, examining the impact on material properties, device structure, and circuit-level behavior. We explore the role of critical device layers - including barrier and channel engineering, substrate selection, and passivation strategies - in mitigating high-temperature-induced effects, and evaluate the thermal stability of III-nitride HEMTs in logic, radiofrequency, and power electronics applications. We also highlight key remaining challenges in the design and optimization of III-nitride devices for high-temperature applications.

cond-mat.mtrl-sci↗

arXiv2025

High Breakdown Electric Field (> 5 MV/cm) in UWBG AlGaN Transistors

We report on the design and demonstration of ultra-wide bandgap (UWBG) AlGaN-channel metal-insulator heterostructure field effect transistors (HEFTs) for high-power, high-frequency applications. We find that the integration of gate dielectrics and field plates greatly improves the breakdown field in these devices, with state-of-art average breakdown field of 5.3 MV/cm (breakdown voltage > 260 V) with an associated maximum current density of 342 mA/mm, and cut-off frequency of 9.1 GHz. Furthermore, low trap-related impact was observed from minimal gate and drain lag estimated from pulsed I-V characteristics. The reported results provide the potential of UWBG AlGaN HEFTs for the next generation high-power radio frequency applications.

cond-mat.mtrl-sci↗

arXiv2019

Using Floating Gate Memory to Train Ideal Accuracy Neural Networks

Floating gate SONOS (Silicon-Oxygen-Nitrogen-Oxygen-Silicon) transistors can be used to train neural networks to ideal accuracies that match those of floating point digital weights on the MNIST dataset when using multiple devices to represent a weight or within 1% of ideal accuracy when using a single device. This is enabled by operating devices in the subthreshold regime, where they exhibit symmetric write nonlinearities. A neural training accelerator core based on SONOS with a single device per weight would increase energy efficiency by 120X, operate 2.1X faster and require 5X lower area than an optimized SRAM based ASIC.

cs.ET↗

arXiv2018

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator

Neural networks are an increasingly attractive algorithm for natural language processing and pattern recognition. Deep networks with >50M parameters are made possible by modern GPU clusters operating at <50 pJ per op and more recently, production accelerators capable of <5pJ per operation at the board level. However, with the slowing of CMOS scaling, new paradigms will be required to achieve the next several orders of magnitude in performance per watt gains. Using an analog resistive memory (ReRAM) crossbar to perform key matrix operations in an accelerator is an attractive option. This work presents a detailed design using a state of the art 14/16 nm PDK for of an analog crossbar circuit block designed to process three key kernels required in training and inference of neural networks. A detailed circuit and device-level analysis of energy, latency, area, and accuracy are given and compared to relevant designs using standard digital ReRAM and SRAM operations. It is shown that the analog accelerator has a 270x energy and 540x latency advantage over a similar block utilizing only digital ReRAM and takes only 11 fJ per multiply and accumulate (MAC). Compared to an SRAM based accelerator, the energy is 430X better and latency is 34X better. Although training accuracy is degraded in the analog accelerator, several options to improve this are presented. The possible gains over a similar digital-only version of this accelerator block suggest that continued optimization of analog resistive memories is valuable. This detailed circuit and device analysis of a training accelerator may serve as a foundation for further architecture-level studies.

cs.AR↗