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arXiv · 1908.07942

Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator

Insik Yoon·Matthew Jerry·Suman Datta·Arijit Raychowdhury
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Abstract

In this letter, we quantify the impact of device limitations on the classification accuracy of an artificial neural network, where the synaptic weights are implemented in a Ferroelectric FET (FeFET) based in-memory processing architecture. We explore a design-space consisting of the resolution of the analog-to-digital converter, number of bits per FeFET cell, and the neural network depth. We show how the system architecture, training models and overparametrization can address some of the device limitations.

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Insik Yoon, Matthew Jerry, Suman Datta, Arijit Raychowdhury. 2019-08-12. Design space exploration of Ferroelectric FET based Processing-in-Memory DNN Accelerator. https://arxiv.org/abs/1908.07942

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