On the Hardness of the Determinant: Sum of Regular Set-Multilinear Circuits

S Raja; Sumukha Bharadwaj G V

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arXiv · 2109.10094

On the Hardness of the Determinant: Sum of Regular Set-Multilinear Circuits

S Raja·Sumukha Bharadwaj G V

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Abstract

In this paper, we study the computational complexity of the commutative determinant polynomial computed by a class of set-multilinear circuits which we call regular set-multilinear circuits. Regular set-multilinear circuits are commutative circuits with a restriction on the order in which they can compute polynomials. A regular circuit can be seen as the commutative analogue of the ordered circuit defined by Hrubes,Wigderson and Yehudayoff [HWY10]. We show that if the commutative determinant polynomial has small representation in the sum of constantly many regular set-multilinear circuits, then the commutative permanent polynomial also has a small arithmetic circuit.

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BibTeX RIS

S Raja, Sumukha Bharadwaj G V. 2021-09-21. On the Hardness of the Determinant: Sum of Regular Set-Multilinear Circuits. https://arxiv.org/abs/2109.10094

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