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arXiv · 2206.04108

Modeling Defect-Level Switching for Highly-Nonlinear and Hysteretic Electronic Devices

Jiahao Dong·R. Jaramillo
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Abstract

Previously, we demonstrated hysteretic and persistent changes of resistivity in two-terminal electronic devices based on charge trapping and detrapping at immobile metastable defects [H. Yin, A. Kumar, J.M. LeBeau, and R. Jaramillo, Phys. Rev. Applied 15, 014014 (2021)]; we termed these devices as defect-level switching (DLS) devices. DLS devices feature all-electronic resistive switching and thus are volatile because of the voltage-time dilemma. However, the dynamics of volatile resistive switches may be valuable for emerging applications such as selectors in crosspoint memory, and neuromorphic computing concepts. To design memory and computing circuits using these volatile resistive switches, accurate modeling is essential. In this work we develop an accurate and analytical model to describe the switching physics in DLS devices, based on the established theories of point defect metastability in Cu(In,Ga)Se2 (CIGS) and II-VI semiconductors. The analytical nature of our model allows for time-efficient simulations of dynamic behavior of DLS devices. We model the time durations of SET and RESET programming pulses, which can be exponentially shortened with respect to the pulse amplitude. We also demonstrate the concept of inverse design: given desired resistance states, the width and amplitude of the programming signal can be chosen accordingly.

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BibTeXRIS

Jiahao Dong, R. Jaramillo. 2022-06-02. Modeling Defect-Level Switching for Highly-Nonlinear and Hysteretic Electronic Devices. https://doi.org/10.1063/5.0197121

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