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arXiv · 2309.01615

A balanced Memristor-CMOS ternary logic family and its application

Xiao-Yuan Wang·Jia-Wei Zhou·Chuan-Tao Dong·Xin-Hui Chen·Sanjoy Kumar Nandi·Robert G. Elliman·Sung-Mo Kang·Herbert Ho-Ching Iu
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Abstract

The design of balanced ternary digital logic circuits based on memristors and conventional CMOS devices is proposed. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are systematically designed and verified by simulation, and then logic circuits such as ternary encoders, decoders and multiplexers are designed on this basis. Two different schemes are then used to realize the design of functional combinational logic circuits such as a balanced ternary half adder, multiplier, and numerical comparator. Finally, we report a series of comparisons and analyses of the two design schemes, which provide a reference for subsequent research and development of three-valued logic circuits.

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Xiao-Yuan Wang, Jia-Wei Zhou, Chuan-Tao Dong, Xin-Hui Chen, Sanjoy Kumar Nandi, Robert G. Elliman, Sung-Mo Kang, Herbert Ho-Ching Iu. 2023-09-04. A balanced Memristor-CMOS ternary logic family and its application. https://arxiv.org/abs/2309.01615

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