xeSFQ: Clockless SFQ Logic with Zero Static Power

Abstract

ERSFQ circuits eliminate the dominant portion of static power consumption in RSFQ circuits by using current-limiting Josephson junctions and inductors instead of bias resistors. In practice, these junctions still contribute to static power consumption through switching required to correct phase imbalances across the circuit, with their contributions sometimes comparable to dynamic power. This paper presents a new SFQ family variant, called xeSFQ, that combines the clock-free alternating SFQ logic with ERSFQ's biasing. By ensuring a single pulse per line per logical cycle, xeSFQ eliminates even the residual switching due to phase imbalance, achieving truly zero static power consumption. Detailed analog simulations and synthesis results for various circuits, from single gates to ISCAS85 and EPFL benchmarks, validate the above hypothesis and showcase the all-around benefits of the proposed approach.