arXiv subjects

Jennifer Volk

Publications and source records attributed to Jennifer Volk.

4 recordsLinked to original sources

arXiv2024

xeSFQ: Clockless SFQ Logic with Zero Static Power

ERSFQ circuits eliminate the dominant portion of static power consumption in RSFQ circuits by using current-limiting Josephson junctions and inductors instead of bias resistors. In practice, these junctions still contribute to static power consumption through switching required to correct phase imbalances across the circuit, with their contributions sometimes comparable to dynamic power. This paper presents a new SFQ family variant, called xeSFQ, that combines the clock-free alternating SFQ logic with ERSFQ's biasing. By ensuring a single pulse per line per logical cycle, xeSFQ eliminates even the residual switching due to phase imbalance, achieving truly zero static power consumption. Detailed analog simulations and synthesis results for various circuits, from single gates to ISCAS85 and EPFL benchmarks, validate the above hypothesis and showcase the all-around benefits of the proposed approach.

physics.app-ph↗

arXiv2024

Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic

Gate-level clocking, typical in traditional approaches to Single Flux Quantum (SFQ) technology, makes the effective synthesis of superconducting circuits a significant engineering hurdle. This paper addresses this challenge by employing the recently introduced alternating SFQ (xSFQ) logic family. xSFQ leverages dual-rail alternating encoding to eliminate the clock dependency from the superconducting gate semantics. This obviates the need for ad hoc modifications to existing synthesis tools and avoids unnecessary circuit resource overheads, marking a significant advancement in superconducting circuit design automation. Our implementation results demonstrate an average reduction of over 80\% in the Josephson junction count for circuits from the ISCAS85, EPFL, and ISCAS89 benchmark suites.

cs.AR↗

arXiv2023

Addressable Superconductor Integrated Circuit Memory from Delay Lines

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 GHz and 100 GHz, with $\pm$24\% and $\pm$13\% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm$^2$ with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm$^2$ and beyond

cs.ET↗

arXiv2023

Low-Cost Superconducting Fan-Out with Cell I$_\text{C}$ Ranking

Superconductor electronics (SCE) promise computer systems with orders of magnitude higher speeds and lower energy consumption than their complementary metal-oxide semiconductor (CMOS) counterparts. At the same time, the scalability and resource utilization of superconducting systems are major concerns. Some of these concerns come from device-level challenges and the gap between SCE and CMOS technology nodes, and others come from the way Josephson Junctions (JJs) are used. Towards this end, we notice that a considerable fraction of hardware resources are not involved in logic operations, but rather are used for fan-out and buffering purposes. In this paper, we ask if there is a way to reduce these overheads, propose the use of JJs at the cell boundaries to increase the number of outputs that a single stage can drive, and establish a set of rules to discretize critical currents in a way that is conducive to this assignment. Finally, we explore the design trade-offs that the presented approach opens up and demonstrate its promise through detailed analog simulations and modeling analyses. Our experiments indicate that the introduced method leads to a 48% savings in the JJ count for a tree with a fan-out of 1024, as well as an average of 43% of the JJ count for signal splitting and 32% for clock splitting in ISCAS'85 benchmarks.

cs.ET↗