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arXiv · 2509.15388

Development of BPM electronics for PIP-II at Fermilab

Shengli Liu·Nathan Eddy·A. Semenov·Brian Fellenz
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Abstract

This paper presents the uTCA4.0-based BPM electronics for PIP-II, featuring four 250 MSPS ADCs and a Xilinx UltraScale+ MPSoC FPGA with 10 GbE uplink. Design elements include signal conditioning, clock, and thermal management. The FPGA performs signal processing, time tagging, digital down-conversion, and phase drift compensation. Position and phase resolution, and thermal stability - is validated through dedicated testing.

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Shengli Liu, Nathan Eddy, A. Semenov, Brian Fellenz. 2025-09-18. Development of BPM electronics for PIP-II at Fermilab. https://arxiv.org/abs/2509.15388

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