A CMOS+X Spiking Neuron With On-Chip Machine Learning

Abstract

We present the design and numerical simulation of a spiking neuron in a proof-of-concept model of on-chip machine learning. Built within the CMOS+X framework, the spiking neuron consists of an NMOS transistor combined with a magnetic tunnel junction (MTJ). This NMOS+MTJ unit, when simulated in the industry-standard circuit simulation software ``LTspice'', reproduces multiple functions of a biological neuron, including threshold spiking, latency, refractory periods, synaptic integration, and inhibition. These behaviors arise from the intrinsic magnetization dynamics of the MTJ and do not require any additional control circuitry. By interconnecting the NMOS+MTJ neurons, we construct a model of an analog multilayer network that learns through spike-timing-dependent weight updates derived from a gradient-descent rule, with both training and inference modeled in the analog domain. The simulated network demonstrates spike propagation and successful training on the XOR task under the modeled conditions.