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arXiv · 2512.08086

Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics

Arup Singha·Shaili Sett·Kenji Watanabe·Takashi Taniguchi·Arindam Ghosh·Rahul Debnath
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Abstract

Long-range moire patterns in twisted WSe2 enable a built-in, moire-length-scale ferroelectric polarization that can be directly harnessed in electronic devices. Such a built-in ferroic landscape offers a compelling means to enable ultralow-voltage and non-volatile electronic functionality in two-dimensional materials; however, achieving stable polarization control without charge trapping has remained a persistent challenge. Here, we demonstrate a moire-engineered ferroelectric field-effect transistor (FeFET) utilizing twisted WSe2 bilayers that leverages atomically clean van der Waals interfaces to achieve efficient polarization-channel coupling and trap-suppressed, ultralow-voltage operation (subthreshold swing of 64 mV per decade). The device exhibits a stable non-volatile memory window of 0.10 V and high mobility, exceeding the performance of previously reported two-dimensional FeFET and matching that of advanced silicon-based devices. In addition, capacitance-voltage spectroscopy, corroborated by self-consistent Landau-Ginzburg-Devonshire modeling, indicates ultrafast ferroelectric switching (~0.5 microseconds). These results establish moire-engineered ferroelectricity as a practical and scalable route toward ultraclean, low-power, and non-volatile 2D electronics, bridging atomistic lattice engineering with functional device architectures for next-generation memory and logic technologies.

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Arup Singha, Shaili Sett, Kenji Watanabe, Takashi Taniguchi, Arindam Ghosh, Rahul Debnath. 2025-12-08. Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics. https://arxiv.org/abs/2512.08086

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