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arXiv · 2606.04629

Circuit-Level Noise Estimation via Shuttling in Plaquette Circuits

Huyen Do·Alexandru Paler
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Abstract

We present a method for estimating QEC circuit-level noise levels assuming that only single-shot measurements are available (e.g. measurements are slow and performed in a zoned/parallel fashion), and that lower level quantum hardware calibration is not possible (e.g. cloud access) or not feasible (e.g. large scale computing). We develop and run surface code plaquette experiments using two syndrome qubit configurations: FRESH, involving fresh qubits for each plaquette repetition, and RECYCLE, reusing qubits. To validate our approach, we compile plaquettes to ion-trap (IonQ Aria1) native gate set and apply hardware-aware rewrite templates to reduce circuit depth and execution time. We also run the experiments on a non-shuttling, superconducting processor (IBM Torino). We estimate circuit-level noise rates from the resulting single-shot plaquette measurement statistics, and conclude numerically about the viability of low-depth QEC experiments.

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Huyen Do, Alexandru Paler. 2026-06-03. Circuit-Level Noise Estimation via Shuttling in Plaquette Circuits. https://arxiv.org/abs/2606.04629

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