Spatiotemporally Interleaved Homodyne Photonic Tensor Core

Abstract

Photonic computing provides ultrahigh bandwidth, low latency and intrinsic parallelism, making it a promising route beyond the scaling limits of electronic computing. However, existing on-chip photonic computing systems remain constrained by persistent trade-offs among high-speed modulation, energy efficiency and large-scale integration, limiting their system-level advantages. Here we present a spatiotemporally interleaved homodyne photonic tensor core implemented on a thin-film lithium niobate (TFLN) platform. By integrating a homodyne photonic matrix with a bus-readout time-integrating array, this architecture scales down the high-speed digital-to-analog and electro-optic interconversion hardware overhead required for photonic matrix operations from O(n^2) to O(n), thereby unlocking system-level scalability. Moreover, the architecture employs orthogonal horizontal and vertical crossbars to route data and weight signals independently, eliminating the intrinsic beam combining loss while enabling ultrahigh-speed synchronous updates of both data and weights. Collectively, these features provide a scalable and hardware-efficient foundation for high-bandwidth photonic processors targeting general-purpose artificial intelligence (AI) computing.