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De-Hui Huang

Publications and source records attributed to De-Hui Huang.

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A Chip-scale Space-time Multiplexed Gaussian Boson Sampling Processor Beyond 10,000 Photons

Gaussian boson sampling (GBS) has emerged as a leading photonic paradigmfor demonstrating quantum computational advantage. Nevertheless, state-ofthe-art GBS setups face practical barriers including stringent optical alignment, phase instability, and limited programmability, which impede scalable engineering deployment. The chip-scale space-time multiplexed architecturepromises to resolve these constraints, yet it strongly demands wafer-scale chipcapabilities to simultaneously satisfy stringent requirements on low loss, highprecision and high-speed modulation. Here we report the first chip-scale spacetime multiplexed GBS system, monolithically integrating high-speed electrooptic modulators, on-chip delay lines, and a time-space multiplexed interferometric network on a thin-film lithium niobate chip, operating at a 4-GHz clockrate with detection events of up to 11,059 photons within 1 millisecond. Beyond benchmarking quantum advantage, we further reconfigure the photonichardware into a GBS-powered world model for modelling physical dynamics,which achieves lower prediction error with fewer trainable readout parameters compared with a classical echo state network (ESN) baseline. Our resultsvalidate the feasibility of our endeavor towards scalable photonic quantumhardware, and pave the way for the versatile programmable applications offuture GBS quantum systems.

quant-ph

Spatiotemporally Interleaved Homodyne Photonic Tensor Core

Photonic computing provides ultrahigh bandwidth, low latency and intrinsic parallelism, making it a promising route beyond the scaling limits of electronic computing. However, existing on-chip photonic computing systems remain constrained by persistent trade-offs among high-speed modulation, energy efficiency and large-scale integration, limiting their system-level advantages. Here we present a spatiotemporally interleaved homodyne photonic tensor core implemented on a thin-film lithium niobate (TFLN) platform. By integrating a homodyne photonic matrix with a bus-readout time-integrating array, this architecture scales down the high-speed digital-to-analog and electro-optic interconversion hardware overhead required for photonic matrix operations from O(n^2) to O(n), thereby unlocking system-level scalability. Moreover, the architecture employs orthogonal horizontal and vertical crossbars to route data and weight signals independently, eliminating the intrinsic beam combining loss while enabling ultrahigh-speed synchronous updates of both data and weights. Collectively, these features provide a scalable and hardware-efficient foundation for high-bandwidth photonic processors targeting general-purpose artificial intelligence (AI) computing.

physics.optics