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arXiv · 2607.10788

Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits

Ramya Karri·Srija Rasoori·Ashiq A. Sakib
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Abstract

Pre-Charge Half Buffer (PCHB) is a promising asynchronous digital design paradigm for harsh-environment operation; however, its soft-error characteristics remain largely unexplored. This paper presents a systematic soft-error characterization and hardening trade-off analysis for static PCHB circuits. A controlled transistor-level fault-injection framework is developed to extract polarity-dependent critical charge at internal nodes. Vulnerability nodes are identified based on extensive simulation. Four mitigation strategies, double-sided Schmitt trigger, single-sided Schmitt trigger, transmission-gate reinforcement, and duplication-based redundancy, are implemented and evaluated across five representative PCHB cells. Comprehensive resilience-overhead comparisons in delay, energy, and area are reported, leading to architecture-specific hardening guidelines for robust static PCHB design.

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Ramya Karri, Srija Rasoori, Ashiq A. Sakib. 2026-07-12. Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits. https://arxiv.org/abs/2607.10788

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