arXiv subjects

Ashiq A. Sakib

Publications and source records attributed to Ashiq A. Sakib.

3 recordsLinked to original sources

arXiv2026

Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits

Pre-Charge Half Buffer (PCHB) is a promising asynchronous digital design paradigm for harsh-environment operation; however, its soft-error characteristics remain largely unexplored. This paper presents a systematic soft-error characterization and hardening trade-off analysis for static PCHB circuits. A controlled transistor-level fault-injection framework is developed to extract polarity-dependent critical charge at internal nodes. Vulnerability nodes are identified based on extensive simulation. Four mitigation strategies, double-sided Schmitt trigger, single-sided Schmitt trigger, transmission-gate reinforcement, and duplication-based redundancy, are implemented and evaluated across five representative PCHB cells. Comprehensive resilience-overhead comparisons in delay, energy, and area are reported, leading to architecture-specific hardening guidelines for robust static PCHB design.

cs.AR↗

arXiv2025

HALOC-AxA: An Area/-Energy-Efficient Approximate Adder for Image Processing Application

The design of approximate adders has been widely researched to advance energy-efficient hardware for computation-intensive multimedia applications, such as image, audio, or video processing. The design of approximate adders has been widely researched to advance energy-efficient hardware for computation intensive multimedia applications, such as image/audio/video processing. Several static and dynamic approximate adders exist in the literature, each of which endeavors to balance the conflicting demands of high performance, computational accuracy, and energy efficiency. This work introduces a novel approximate adder that is more energy- and area-efficient than existing adders, while achieving improved or comparable accuracy, as demonstrated by simulation results. The proposed adder's ability to digitally reconstruct high quality images is further demonstrated by the deployment of the design for an image processing task.

cs.AR↗

arXiv2025

SR-NCL: an Area-/Energy-Efficient Resilient NCL Architecture Based on Selective Redundancy

Duplication-based redundancy schemes have proven to be effective in designing fully-resilient Quasi-delay Insensitive (QDI) asynchronous circuits. The complete resiliency, however, is accompanied by significant energy, latency, and area overhead. This paper presents a novel error-tolerant Null Convention Logic (NCL) architecture based on selective redundancy. Results demonstrate the efficacy of the proposed method in terms of area and energy utilization as compared to existing duplication-based NCL designs, targeting an image processing application.

cs.AR↗