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arXiv · 2608.01239

Smart membrane: high content in situ monitoring barrier on chip with artificial neural network

Abstract

Conventional transepithelial electrical resistance (TEER) technique provides only a low-content analysis of cell-layer conditions, necessitating repeated microscopic assessments of morphology and cell-cell contacts outside the incubator for barrier-on-chip systems. This work presents a novel high-content TEER device in the form of a novel nanoporous membrane that facilitates continuous electrical measurement of cell-substrate impedance sensing (ECIS). The ultrathin (700 nm) membrane, composed of ultra-low-stress SixNy, is monolithically integrated into wafer-level fabricated chips sealed with glass lids. Coplanar ECIS electrodes were connected to custom electronics to record impedance under sinusoidal excitation. Human umbilical vein endothelial cells (HUVECs) were seeded and continuously recorded impedance spectra were compared with bright-field and fluorescence microscopy, revealing distinct phases of monolayer formation. With one-dimensional convolutional neural network (Conv1d) and Kolmogorov-Arnold Network (KAN) trained with a small amount of Nyquist-diagrams, phases of (I) adherence, (II) outspreading, (III) confluence and (IV) barrier maturity with tight junction formation could be recognized with 95% confidence. As further proof of concept, reversible and irreversible barrier weakening using modulators PN159 and BAC was identified in this way. Our studies have demonstrated that an immediate and automatable non-invasive detection of in-vitro barrier dynamics within barrier-on-chip systems, eliminating the need for microscopy and endpoint staining. We expect this ECIS technique will find broad applications in organ-on-chip systems for in situ monitoring physiological or pathological states of tissue barrier.

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Bo Tang, Victor Krajka, Mengxi Liu, Wei Zhao, Gazal Goekkus, Paul Lukowicz, Lili Zhu, Pu Chen, Stephan Reichl, Andreas Dietzel. 2026-08-02. Smart membrane: high content in situ monitoring barrier on chip with artificial neural network. https://arxiv.org/abs/2608.01239

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