A 188-260 GHz Distributed Frequency Multiplier Achieving 4 dBm Saturated Output Power in 65 nm CMOS

Abstract

Sub-terahertz (sub-THz) low-phase-noise signal sources commonly employ frequency multiplier chains to extend the operating frequency of lower-frequency oscillators. This paper presents the design and simulations of a wideband, high-output-power frequency multiplier implemented in TSMC 65 nm CMOS technology. The proposed design is based on a distributed frequency multiplier with a quarter-wave transmission line termination at the drain side, where the reflected and forward-traveling waves are constructively combined to enhance the output power. The proposed frequency doubler achieves a minimum conversion loss of 12 dB at an input frequency of 115 GHz with an input power of 12 dBm, resulting in an output power of 0 dBm and 12.6 dB fundamental suppression. For the same input power, the output power remains within 3 dB of its peak value over the 188-260 GHz output frequency range. At 230 GHz, the proposed design achieves a saturated output power of 4 dBm while occupying an area of 0.149 mm^2.