Resolving the Thermal Labyrinth inside 3D-IC Stacks

Abstract

The heat pathways in 3D-ICs have long been a labyrinth lacking experimental investigations into spatial distribution of thermal properties, severely limiting study of internal thermal management inside chips. For the first time, we established a methodology for 3D thermal characterizations of advanced 3D-ICs, implemented through a systematic workflow that enables layer-resolved thermal property extraction and the construction of a location-specific thermal database. We demonstrated its application to an advanced sample featuring 2.2-μm-diameter TSVs and ~2-μm-pitch face-to-face hybrid bonding (HB). Time-domain and steady-state thermoreflectance were used to extract the thermal conductivities (TCs) of Al traces, TSV, BEOL interconnects and HB pads, indicating HB structure enables efficient thermal transport with 9 W/m-K TC. Further, we mapped and visualized the TC distribution of TSV structures and RDL Cu wires with small step sizes down to 0.2 μm. Utilizing these results, we proposed an experiment-based thermal model to reveal that co-evolution of interconnect and substrate TCs is essential for thermal design and fabrication towards effective cooling optimization.