Searcharxiv⌕ Search
Home/Archive/arXiv

arXiv · 2610.37466

Kernel Performance Engineering under Physical Non-Idealities

Supun Kuruppu·Pranav Dangi·Wei Li·Zhenyu Bai·Tulika Mitra
View original source ↗Read source document ↗Export metadata ↓

Abstract

Physical non-idealities in integrated circuit (IC) design and fabrication are concealed by conventional hardware abstractions, yet they can limit kernel performance and obscure optimization opportunities. Using distributed shared memory (DSMEM) on NVIDIA H100 GPUs as a case study, we show how floorsweeping restricts hardware resources available for clustered execution, potentially offsetting the benefits of reduced data movement enabled by DSMEM. Guided by these insights, we develop a wave-aware clustering strategy that accounts for these resource constraints to improve kernel performance. Evaluations using a global-load-and-broadcast microbenchmark, GEMM, and the Hopper version of FlashAttention 4 demonstrate the performance implications of these constraints, with wave-aware clustering improving FlashAttention 4 throughput by up to 5.30% over its baseline. We further show that, under thermal design power (TDP) limits, reduced data movement enables higher Streaming Multiprocessor (SM) frequencies through Dynamic Voltage and Frequency Scaling (DVFS), explaining otherwise unexpected throughput improvements. Extending this analysis beyond GPUs, we show that power constraints also limit throughput scaling on Tenstorrent's Wormhole accelerator, highlighting the broader importance of accounting for physical non-idealities when analyzing and optimizing kernel performance.

Explore related subjects

cs.AR

Keep this discovery

Explore connections, maps & timelines

BibTeXRIS

Supun Kuruppu, Pranav Dangi, Wei Li, Zhenyu Bai, Tulika Mitra. 2026-10-27. Kernel Performance Engineering under Physical Non-Idealities. https://arxiv.org/abs/2610.37466

Cite the original work for its findings. Save a collection to share your selection of sources.

KEEP EXPLORING

Related papers

arXiv2026

A State Augmented Approach to Paralle Modeling in High-Level Synthesis

High-level synthesis (HLS) can schedule only the concurrency made legal by its input description. For feedback-coupled designs, a sequential behavioral model can obscure the architectural state boundaries and hazard resolution needed for efficient overlap. We develop an explicit architectural modeling methodology based on synchronous sequential processes that start in lockstep and synchronize completion before repeating. Persistent state, communication, and feedback control are represented in C++, while HLS schedules and binds operations within that structure. A five-stage RV32I processor illustrates three consequential modeling decisions: which version of a value a consumer reads, when it consumes that value, and how architectural memory actions map to port operations. On a Kintex UltraScale+ FPGA, the CPI-optimized configuration achieves 1.221 cycles per instruction at 220 MHz, compared with 4.000 for an algorithmic HLS baseline and 1.575 at 242 MHz for an Ibex reference. An area-optimized configuration reduces LUTs by 65\% and registers by 47\%, with 9.7\% more benchmark cycles and a 250 MHz achieved clock. These results demonstrate a separation between designer-controlled architecture and tool-controlled scheduling.

cs.AR↗
arXiv2026

Comparative Analysis of Large Load Interconnection Requirements Across U.S. Transmission Entities

The rapid growth of large loads, especially data centers driven by artificial intelligence, is creating unprecedented demands on the North American electric grid. Data centers now account for nearly 80% of large load interconnection requests in the Western Interconnection, and U.S. electricity consumption from data centers is projected to reach 325-580 TWh by 2028. Despite this urgency, technical interconnection requirements for large loads have not yet matured and still contain several gaps. This paper presents a comparative analysis of large load interconnection requirements across eleven U.S. entities, including AEP, Ameren, CAISO, Dominion, Duke Energy, ERCOT, LIPA, MISO, PJM, Southern Company, and SPP, under seven technical categories: large load definition, load data and modeling, fault ride-through, load curtailment and shedding, dispatchability, power quality, and reactive power control. The analysis reveals significant variation in both the scope and specificity of requirements. LIPA addresses all seven technical categories at least partially, while Dominion and Duke Energy provide detailed coverage across nearly all categories. The analysis also finds that data center applicants can be viewed as potential grid resources, rather than only as consumers. The findings provide a structured baseline from which utilities, regulators, ISOs/RTOs, and developers can identify gaps, benchmark against peers, and accelerate the development of interconnection standards.

cs.AR↗
arXiv2026

p-DCIM: A 28nm Probabilistic SRAM DCIM based Ising Machine for Near-Memory Context Selection in LLM-RAG Pipeline

We present a fabricated SRAM DCIM Ising machine that performs set-level context selection for large language model (LLM) with retrieval-augmented generation (RAG). In RAG, the evidence-selection stage is increasingly delegated to repeated language-model reranking, which adds substantial energy to the inference pipeline. We reformulate evidence selection as a quadratic unconstrained binary optimization (QUBO) problem and solve it on a dual-mode digital compute-in-memory (DCIM) macro: the same multiply-and-accumulate datapath computes the embedding-similarity scores that populate the QUBO coefficients and evaluates the per-spin Hamiltonian differences that drive the anneal. The annealing temperature is set by a digital plane-count control along with the SRAM pseudo-read random bit flips, giving graded cooling entirely from on-chip digital configuration. The macro is taped-out in a 28 nm process [0.16 mm2, 0.41 mW] and is proposed to be integrated as part of the logic base-die in hybrid high-bandwidth memory (HBM) and high-bandwidth flash (HBF) stacks in a GPU package, where only the selected passage identifiers return to the host. Replacing the language-model selection pass with the near-memory Ising solver yields a macro normalized selection-energy estimate more than six orders of magnitude lower than the LLM-based baseline and reduces the evaluated total energy per query by 67%, while maintaining comparable token-level F1 on the evaluated examples.

cs.AR↗