Implementation and Validation of Mismatch-Tolerant High-Gain OTA with a Calibrated Negative Conductance Load

Abstract

This paper presents the circuit-level implementation of a mismatch-tolerant high-gain operational transconductance amplifier (OTA) using automatic negative-conductance calibration in 65-nm CMOS. The technique enhances OTA gain by compensating for its finite output conductance using a cross-coupled transistor pair, with an on-chip calibration loop that eliminates the need for a replica circuit or external tuning. The calibration routine increases the gain by driving the steady state error of the OTA in a unity gain feedback loop toward zero. The implementation addresses practical challenges involving comparator offset, DAC design, and subtractor gain and offset. A 6-bit capacitive DAC (CDAC)-based comparator offset calibration scheme enables reliable detection of the sub-millivolt steady state error required for high OTA gain. Post-layout Monte Carlo simulations show that the comparator offset standard deviation is reduced from 4.11 mV to 132 $μ$V, with a maximum observed post-calibration offset of 625 $μ$V. The complete calibration circuitry is implemented and evaluated through post-layout simulations.