Bezier-GP: Bezier-Surface-Based Gaussian Process for Chips-on-Wafer Warpage Modeling

Abstract

As the semiconductor industry transitions to the post-Moore paradigm, wafer warpage has become a critical quality issue in advanced packaging; particularly for 3D stacking and high-bandwidth memory manufacturing where die-level deformation can affect bonding quality, interconnect reliability, and yield. However, direct high-throughput measurement of individual chip warpage remains difficult in mass-production environments, while existing wafer-level metrology systems routinely provide dense 3D shape data at the wafer scale. This paper proposes a Bezier-surface-based Gaussian Process---known as Bezier-GP---for chips-on-wafer warpage modeling. The proposed framework combines wafer-level point-cloud metrology data with wafer-map layout information to construct chip-region-level Bezier surface patches, imposes continuity constraints between neighboring patches, and represents the resulting chips-on-wafer surface through a compact free-control-point vector. A GP is then introduced in this low-dimensional representation to model wafer-to-wafer variation, chip-region-level spatial dependence, and provide uncertainty quantification. Numerical experiments, using an ASC wafer-map layout, demonstrate that the proposed framework can reconstruct chips-on-wafer surfaces, preserve chip-region-level geometric interpretability, and recover population-level mean and covariance structures under a controlled multi-wafer simulation setting. The results suggest that Bezier-GP provides a measurement-driven statistical modeling foundation for connecting wafer-level metrology data to chip-region-level warpage analysis in semiconductor manufacturing.