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Adam Quinn

Publications and source records attributed to Adam Quinn.

7 recordsLinked to original sources
arXiv2026

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

cond-mat.mes-hall↗
arXiv2026

On-Detector Machine Learning for Beam-Induced Background Rejection at a 10 TeV Muon Collider

A 10 TeV Muon Collider is a compelling candidate for a future energy-frontier facility, offering unprecedented opportunities to explore the fundamental laws of particle physics. Muon decays in the collider ring produce intense beam-induced background (BIB) that can overwhelm detector occupancy and exceed readout bandwidth constraints. We investigate the potential of on-detector Machine Learning for BIB rejection in the vertex detector, exploiting pixel cluster shapes to distinguish background from collision products. We study three classes of lightweight neural-network architectures, and evaluate their implementation feasibility using high-level synthesis. Selected architectures achieve 88 to 90% data reduction at 99% signal efficiency, while requiring hardware resources compatible with potential ASIC implementation. These results demonstrate the potential of performing substantial BIB rejection directly in the pixel readout, providing a strategy for meeting the tracker readout requirements at a future Muon Collider.

hep-ex↗
arXiv2025

Characterization of a 28 nm $\textit{smartpixels}$ ASIC With On-Chip ML for Particle Tracking Detectors

We present a 28 nm CMOS pixel readout integrated circuit implementing in-pixel analog signal processing and on-chip machine learning data filtering for particle tracking detectors. Our ASIC comprises two $32 \times 8$ pixel matrices with a pixel pitch of $25 \times 25~\mu\mathrm{m}^2$, in which each pixel integrates a charge-sensitive amplifier with synchronous auto-zero offset cancellation and a 2-bit flash ADC with programmable thresholds. Two analog front-end architectures, single-ended and differential, are implemented and characterized. Digitized pixel data are combined into row-wise projections and processed by an on-chip, fully combinational neural network classifier for data reduction. Measurements at room temperature using charge injection demonstrate an equivalent noise charge of $54.6~\mathrm{e}^{-}$ and a threshold dispersion of $\sim$78.2~\unit{\electron} at nominal bias, linear response up to several~\unit{\kilo\electron}, and stable operation at a 10~MHz clock frequency. The neural network output is compared with offline RTL predictions and agrees for $99.06\%$ of $1.5 \times 10^{5}$ test inputs.

physics.ins-det↗
arXiv2024

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented, along with a demonstrative example of using Spacely to test a pixel detector readout ASIC.

physics.ins-det↗
arXiv2024

A cryogenic readout integrated circuit with analog pile-up and in-Pixel ADC for high frame rate Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is an in-Pixel analog front end and ADC designed for the vertical readout of Skipper CCD-in-CMOS image sensors. SPROCKET2 is fabricated in a 65 nm CMOS process and each pixel occupies a \SI{60}{\micro\meter} $\times$ \SI{60}{\micro\meter} footprint. SPROCKET2 is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor ASIC, such that one readout pixel is connected to a multiplexed array of sixteen \SI{15}{\micro\meter} $\times$ \SI{15}{\micro\meter} Skipper-in-CMOS pixels. In order to fully leverage the Skipper CCD-in-CMOS sensor's ability to achieve exceptionally low noise from repeated sampling while minimizing the power consumption of digitization and data movement, SPROCKET2 is designed to ``pile-up'' ten successive samples in the analog front end before digitizing the result with a compact 10-bit SAR ADC at a rate of 66.7 ksps, leading to an effective throughput of 667 ksps. The SPROCKET2 pixel achieves input-referred noise $ \lt 100 \mu V_{rms}$ with $\lt 1$ LSB ADC non-linearity while consuming an estimated $44 \mu W$ per pixel. A SPROCKET2 test pixel was submitted in December 2022, and test results are presented.

physics.ins-det↗
arXiv2023

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

physics.ins-det↗