arXiv subjects

Advait Madhavan

Publications and source records attributed to Advait Madhavan.

At least 19 recordsLinked to original sources

arXiv2026

Stochastic binary networks with asymmetric and time-delayed interactions

Stochastic binary networks are widely used to describe collective dynamics in complex systems and to perform neuromorphic computation, yet realistic networks often contain both asymmetric interactions and finite signal propagation times that fall outside conventional theories. Here we study stochastic binary networks with asymmetric and time-delayed interactions motivated by experimental observations in coupled superparamagnetic tunnel junctions. We find that time delay fundamentally reshapes the dynamics induced by anti-symmetric couplings, producing strong oscillatory temporal correlations consistent with experiment. At the same time, sufficiently long delays drive the steady-state probabilities toward equal state occupations even in strongly coupled systems. These apparently featureless probability distributions coexist with pronounced temporal correlations, distinguishing them from equilibrium high-temperature behavior. We further show analytically that delay-induced uniform distributions emerge in a broad class of stochastic networks, while symmetry-breaking bias fields restore interaction-dependent steady states with qualitatively modified behavior. Simulations of networks with five coupled spins demonstrate that these effects persist beyond minimal systems with only two spins. Our results establish a unified framework for stochastic binary networks in the intermediate regime between symmetric instantaneous interactions and asymmetric or time-delayed interactions, and suggest that asymmetry and delay can be exploited as functional resources in neuromorphic hardware and complex network dynamics.

physics.app-ph↗

arXiv2026

CMOS-integrated superparamagnetic tunnel junction-based p-bit

Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.

cs.ET↗

arXiv2025

Metrics for spin-based computing

Spin-based computing is emerging as a powerful approach for energy-efficient and high-performance solutions to future data processing hardware. Spintronic devices function by electrically manipulating the collective dynamics of the electron spin, that is inherently non-volatile, nonlinear and fast-operating, and can couple to other degrees of freedom such as photonic and phononic systems. This review explores key advances in integrating magnetic and spintronic elements into computational architectures, ranging from fundamental components like radio-frequency neurons/synapses and spintronic probabilistic-bits to broader frameworks such as reservoir computing and magnetic Ising machines. We discuss hardware-specific and task-dependent metrics to evaluate the computing performance of spin-based components and associate them with physical properties. Finally, we discuss challenges and future opportunities, highlighting the potential of spin-based computing in next-generation technologies.

cond-mat.mes-hall↗

arXiv2025

Wafer-Level Prototyping Tools for CMOS Bioelectronic Sensors

Integrating biology with complementary metal-oxide-semiconductor (CMOS) sensors can enable highly parallel measurements with minimal parasitic effects, significantly enhancing sensitivity. However, realizing this potential often requires overcoming substantial barriers related to design, fabrication, and heterogeneous integration. In this context, we present a comprehensive suite of tools and methods designed for wafer-scale biosensor prototyping that is sensitive, highly parallelizable, and manufacturable. A central component of our approach is a new initiative that allows for open-source multi-project wafers (MPW), giving all participants access to the designs submitted by others. We demonstrate that this strategy not only promotes design reuse but also facilitates advanced back-end-of-line (BEOL) fabrication techniques, improving the manufacturability and process yield of CMOS biosensors. Developing CMOS-based biosensors also involves the challenge of heterogeneous integration, which includes external electrical, mechanical, and fluid layers. We demonstrate simple modular designs that enable such integration for sample delivery and signal readout. Finally, we showcase the effectiveness of our approach in measuring the hybridization of DNA molecules by focusing on data acquisition and machine learning (ML) methods that leverage the parallelism of the sensors to enable robust classification of desirable analyte interactions.

physics.ins-det↗

arXiv2025

Entropy-Assisted Nanosecond stochastic operation in perpendicular superparamagnetic tunnel junctions

We demonstrate a good agreement between mean dwell times measured in 50~nm diameter, perpendicularly magnetized superparamagnetic tunnel junctions (SMTJ), and theoretical predictions based on Langer's theory. Due to a large entropic contribution, the theory yields Arrhenius prefactors in the femtosecond range for the measured junctions, in stark contrast to the typically assumed value of 1~ns. Thanks to the low prefactors, and fine-tuning of the perpendicular magnetic anisotropy, we report measured mean dwell times as low as 2.7~ns under an in-plane applied field at negligible bias voltage. Under a perpendicular applied field, we predict a Meyer-Neldel compensation phenomenon, whereby the prefactor scales like an exponential of the activation energy, in line with the exponential dependence of the measured dwell time on the field. We further predict the occurrence of (sub)nanosecond dwell times as a function of effective anisotropy and junction diameter at zero bias voltage. These findings pave the way towards the development of ultrafast, low-power, unconventional computing schemes operating by leveraging thermal noise in perpendicular SMTJs, which can be scaled down below 20~nm.

cond-mat.mtrl-sci↗

arXiv2025

Sampling from exponential distributions in the time domain with superparamagnetic tunnel junctions

In the superparamagnetic regime, magnetic tunnel junctions switch between two resistance states due to random thermal fluctuations. The dwell time distribution in each state is exponential. We sample this distribution using a temporal encoding scheme, in which information is encoded in the time at which the device switches between its resistance states. We then develop a circuit element known as a probabilistic delay cell that applies an electrical current step to a superparamagnetic tunnel junction and a temporal measurement circuit that measures the timing of the first switching event. Repeated experiments confirm that these times are exponentially distributed. Temporal processing methods then allow us to digitally compute with these exponentially distributed probabilistic delay cells. We describe how to use these circuits in a Metropolis-Hastings stepper and in a weighted random sampler, both of which are computationally intensive applications that benefit from the efficient generation of exponentially distributed random numbers.

cs.ET↗

arXiv2024

Measurement-driven Langevin modeling of superparamagnetic tunnel junctions

Superparamagnetic tunnel junctions are important devices for a range of emerging technologies, but most existing compact models capture only their mean switching rates. Capturing qualitatively accurate analog dynamics of these devices will be important as the technology scales up. Here we present results using a one-dimensional overdamped Langevin equation that captures statistical properties of measured time traces, including voltage histograms, drift and diffusion characteristics as measured with Kramers-Moyal coefficients, and dwell times distributions. While common macrospin models are more physically-motivated magnetic models than the Langevin model, we show that for the device measured here, they capture even fewer of the measured experimental behaviors.

physics.app-ph↗

arXiv2024

Measurement-driven neural-network training for integrated magnetic tunnel junction arrays

The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann bottleneck by performing computation in or near memory. An inevitability of transferring neural networks onto hardware is that non-idealities such as device-to-device variations or poor device yield impact performance. Methods such as hardware-aware training, where substrate non-idealities are incorporated during network training, are one way to recover performance at the cost of solution generality. In this work, we demonstrate inference on hardware neural networks consisting of 20,000 magnetic tunnel junction arrays integrated on a complementary metal-oxide-semiconductor chips that closely resembles market-ready spin transfer-torque magnetoresistive random access memory technology. Using 36 dies, each containing a crossbar array with its own non-idealities, we show that even a small number of defects in physically mapped networks significantly degrades the performance of networks trained without defects and show that, at the cost of generality, hardware-aware training accounting for specific defects on each die can recover to comparable performance with ideal networks. We then demonstrate a robust training method that extends hardware-aware training to statistics-aware training, producing network weights that perform well on most defective dies regardless of their specific defect locations. When evaluated on the 36 physical dies, statistics-aware trained solutions can achieve a mean misclassification error on the MNIST dataset that differs from the software-baseline by only 2 %. This statistics-aware training method could be generalized to networks with many layers that are mapped to hardware suited for industry-ready applications.

cs.ET↗

arXiv2024

Layer Ensemble Averaging for Improving Memristor-Based Artificial Neural Network Performance

Artificial neural networks have advanced due to scaling dimensions, but conventional computing faces inefficiency due to the von Neumann bottleneck. In-memory computation architectures, like memristors, offer promise but face challenges due to hardware non-idealities. This work proposes and experimentally demonstrates layer ensemble averaging, a technique to map pre-trained neural network solutions from software to defective hardware crossbars of emerging memory devices and reliably attain near-software performance on inference. The approach is investigated using a custom 20,000-device hardware prototyping platform on a continual learning problem where a network must learn new tasks without catastrophically forgetting previously learned information. Results demonstrate that by trading off the number of devices required for layer mapping, layer ensemble averaging can reliably boost defective memristive network performance up to the software baseline. For the investigated problem, the average multi-task classification accuracy improves from 61 % to 72 % (< 1 % of software baseline) using the proposed approach.

cs.ET↗

arXiv2023

Programmable electrical coupling between stochastic magnetic tunnel junctions

Superparamagnetic tunnel junctions (SMTJs) are promising sources of randomness for compact and energy efficient implementations of probabilistic computing techniques. Augmenting an SMTJ with electronic circuits, to convert the random telegraph fluctuations of its resistance state to stochastic digital signals, gives a basic building block known as a probabilistic bit or $p$-bit. Though scalable probabilistic computing methods connecting $p$-bits have been proposed, practical implementations are limited by either minimal tunability or energy inefficient microprocessors-in-the-loop. In this work, we experimentally demonstrate the functionality of a scalable analog unit cell, namely a pair of $p$-bits with programmable electrical coupling. This tunable coupling is implemented with operational amplifier circuits that have a time constant of approximately 1us, which is faster than the mean dwell times of the SMTJs over most of the operating range. Programmability enables flexibility, allowing both positive and negative couplings, as well as coupling devices with widely varying device properties. These tunable coupling circuits can achieve the whole range of correlations from $-1$ to $1$, for both devices with similar timescales, and devices whose time scales vary by an order of magnitude. This range of correlation allows such circuits to be used for scalable implementations of simulated annealing with probabilistic computing.

cs.ET↗

arXiv2023

Unbiased Random Number Generation using Injection-Locked Spin-Torque Nano-Oscillators

Unbiased sources of true randomness are critical for the successful deployment of stochastic unconventional computing schemes and encryption applications in hardware. Leveraging nanoscale thermal magnetization fluctuations provides an efficient and almost cost-free means of generating truly random bitstreams, distinguishing them from predictable pseudo-random sequences. However, existing approaches that aim to achieve randomness often suffer from bias, leading to significant deviations from equal fractions of 0 and 1 in the bitstreams and compromising their inherent unpredictability. This study presents a hardware approach that capitalizes on the intrinsic balance of phase noise in an oscillator injection locked at twice its natural frequency, leveraging the stability of this naturally balanced physical system. We demonstrate the successful generation of unbiased and truly random bitstreams through extensive experimentation. Our numerical simulations exhibit excellent agreement with the experimental results, confirming the robustness and viability of our approach.

cond-mat.mtrl-sci↗

arXiv2022

Associative Memories Using Complex-Valued Hopfield Networks Based on Spin-Torque Oscillator Arrays

Simulations of complex-valued Hopfield networks based on spin-torque oscillators can recover phase-encoded images. Sequences of memristor-augmented inverters provide tunable delay elements that implement complex weights by phase shifting the oscillatory output of the oscillators. Pseudo-inverse training suffices to store at least 12 images in a set of 192 oscillators, representing 16$\times$12 pixel images. The energy required to recover an image depends on the desired error level. For the oscillators and circuitry considered here, 5 % root mean square deviations from the ideal image require approximately 5 $μ$s and consume roughly 130 nJ. Simulations show that the network functions well when the resonant frequency of the oscillators can be tuned to have a fractional spread less than $10^{-3}$, depending on the strength of the feedback.

cs.ET↗

arXiv2022

Implementation of a Binary Neural Network on a Passive Array of Magnetic Tunnel Junctions

The increasing scale of neural networks and their growing application space have produced demand for more energy- and memory-efficient artificial-intelligence-specific hardware. Avenues to mitigate the main issue, the von Neumann bottleneck, include in-memory and near-memory architectures, as well as algorithmic approaches. Here we leverage the low-power and the inherently binary operation of magnetic tunnel junctions (MTJs) to demonstrate neural network hardware inference based on passive arrays of MTJs. In general, transferring a trained network model to hardware for inference is confronted by degradation in performance due to device-to-device variations, write errors, parasitic resistance, and nonidealities in the substrate. To quantify the effect of these hardware realities, we benchmark 300 unique weight matrix solutions of a 2-layer perceptron to classify the Wine dataset for both classification accuracy and write fidelity. Despite device imperfections, we achieve software-equivalent accuracy of up to 95.3 % with proper tuning of network parameters in 15 x 15 MTJ arrays having a range of device sizes. The success of this tuning process shows that new metrics are needed to characterize the performance and quality of networks reproduced in mixed signal hardware.

cs.ET↗

arXiv2021

Mutual control of stochastic switching for two electrically coupled superparamagnetic tunnel junctions

Superparamagnetic tunnel junctions (SMTJs) are promising sources for the randomness required by some compact and energy-efficient computing schemes. Coupling SMTJs gives rise to collective behavior that could be useful for cognitive computing. We use a simple linear electrical circuit to mutually couple two SMTJs through their stochastic electrical transitions. When one SMTJ makes a thermally induced transition, the voltage across both SMTJs changes, modifying the transition rates of both. This coupling leads to significant correlation between the states of the two devices. Using fits to a generalized Néel-Brown model for the individual thermally bistable magnetic devices, we can accurately reproduce the behavior of the coupled devices with a Markov model.

cond-mat.mes-hall↗

arXiv2020

Temporal State Machines: Using temporal memory to stitch time-based graph computations

Race logic, an arrival-time-coded logic family, has demonstrated energy and performance improvements for applications ranging from dynamic programming to machine learning. However, the ad hoc mappings of algorithms into hardware result in custom architectures making them difficult to generalize. We systematize the development of race logic by associating it with the mathematical field called tropical algebra. This association between the mathematical primitives of tropical algebra and generalized race logic computations guides the design of temporally coded tropical circuits. It also serves as a framework for expressing high level timing-based algorithms. This abstraction, when combined with temporal memory, allows for the systematic generalization of race logic by making it possible to partition feed-forward computations into stages and organizing them into a state machine. We leverage analog memristor-based temporal memories to design a such a state machine that operates purely on time-coded wavefronts. We implement a version of Dijkstra's algorithm to evaluate this temporal state machine. This demonstration shows the promise of expanding the expressibility of temporal computing to enable it to deliver significant energy and throughput advantages.

cs.ET↗

arXiv2020

Temporal Memory with Magnetic Racetracks

Race logic is a relative timing code that represents information in a wavefront of digital edges on a set of wires in order to accelerate dynamic programming and machine learning algorithms. Skyrmions, bubbles, and domain walls are mobile magnetic configurations (solitons) with applications for Boolean data storage. We propose to use current-induced displacement of these solitons on magnetic racetracks as a native temporal memory for race logic computing. Locally synchronized racetracks can spatially store relative timings of digital edges and provide non-destructive read-out. The linear kinematics of skyrmion motion, the tunability and low-voltage asynchronous operation of the proposed device, and the elimination of any need for constant skyrmion nucleation make these magnetic racetracks a natural memory for low-power, high-throughput race logic applications.

physics.app-ph↗

arXiv2020

Storing and retrieving wavefronts with resistive temporal memory

We extend the reach of temporal computing schemes by developing a memory for multi-channel temporal patterns or "wavefronts." This temporal memory re-purposes conventional one-transistor-one-resistor (1T1R) memristor crossbars for use in an arrival-time coded, single-event-per-wire temporal computing environment. The memristor resistances and the associated circuit capacitances provide the necessary time constants, enabling the memory array to store and retrieve wavefronts. The retrieval operation of such a memory is naturally in the temporal domain and the resulting wavefronts can be used to trigger time-domain computations. While recording the wavefronts can be done using standard digital techniques, that approach has substantial translation costs between temporal and digital domains. To avoid these costs, we propose a spike timing dependent plasticity (STDP) inspired wavefront recording scheme to capture incoming wavefronts. We simulate these designs with experimentally validated memristor models and analyze the effects of memristor non-idealities on the operation of such a memory.

cs.ET↗

arXiv2020

Energy-efficient stochastic computing with superparamagnetic tunnel junctions

Superparamagnetic tunnel junctions (SMTJs) have emerged as a competitive, realistic nanotechnology to support novel forms of stochastic computation in CMOS-compatible platforms. One of their applications is to generate random bitstreams suitable for use in stochastic computing implementations. We describe a method for digitally programmable bitstream generation based on pre-charge sense amplifiers. This generator is significantly more energy efficient than SMTJ-based bitstream generators that tune probabilities with spin currents and a factor of two more efficient than related CMOS-based implementations. The true randomness of this bitstream generator allows us to use them as the fundamental units of a novel neural network architecture. To take advantage of the potential savings, we codesign the algorithm with the circuit, rather than directly transcribing a classical neural network into hardware. The flexibility of the neural network mathematics allows us to adapt the network to the explicitly energy efficient choices we make at the device level. The result is a convolutional neural network design operating at $\approx$ 150 nJ per inference with 97 % performance on MNIST -- a factor of 1.4 to 7.7 improvement in energy efficiency over comparable proposals in the recent literature.

cs.ET↗