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arXiv · 2604.14446

CMOS-integrated superparamagnetic tunnel junction-based p-bit

Ju-Young Yoon·Nuno Cacoilo·Advait Madhavan·Jabez J. McClelland·Shun Kanai·Hideo Ohno·Shunsuke Fukami·William A. Borders
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Abstract

Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.

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Ju-Young Yoon, Nuno Cacoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, William A. Borders. 2026-04-15. CMOS-integrated superparamagnetic tunnel junction-based p-bit. https://arxiv.org/abs/2604.14446

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