arXiv subjects

Ahmet Efe

Publications and source records attributed to Ahmet Efe.

8 recordsLinked to original sources

arXiv2026

Ising Acceleration for Multi-Robot Multi-Target Planning

Ising machines are emerging as promising hardware for combinatorial optimization. With recent advances in CMOS Ising technology, they are becoming attractive as low-power accelerator systems for robotics, where energy is limited and combinatorial optimization arises in multiple forms. However, a hardware-aware analysis of where such chips fit within a robotics planning stack is still missing. This paper studies the capabilities and limitations of CMOS Ising machines for low-power acceleration in multi-robot multi-target planning. We analyze three planning layers---target sharing, tour construction, and pathfinding---using real 45-spin all-to-all connected CMOS Ising chips as representative devices. We propose new Ising-based planning methods and a multi-mapping pipeline that uses spin merging, coefficient quantization, and spin-budget branching to adapt subproblems to spin- and coefficient-limited hardware. Our results show that the proposed recursive target-sharing method naturally matches the Ising hardware, achieving up to 8,000x lower energy than a classical baseline. End to end, the Ising pipeline produces routes within 9% of a strong classical baseline at 130x lower energy, showing that compact CMOS Ising machines can be effective in selected parts of the planning stack.

cs.ET↗

arXiv2026

Breaking Local-Minimum Traps in Spiking Neural Network-Based Solvers for CSPs via Parallel Tempering

Spiking neural networks (SNNs) with stochastic neurons can solve constraint satisfaction problems (CSPs) by encoding constraints via connectivity and performing probabilistic search via spike dynamics. However, fixed-temperature stochastic dynamics often get trapped in local minima - near-satisfying configurations - a vulnerability that escalates with problem difficulty. To overcome this, we integrate parallel tempering (PT) into the neural sampling solver, running multiple parallel replicas at varying inverse temperatures. Replicas periodically exchange temperatures rather than network states, managing the trade-off between exploration and concentration around low-energy configurations while preserving asynchronous, spike-based computation. We evaluate this architecture against a parallel baseline of four independent, fixed-temperature solvers using equal computational resources across 1000 instances from the SATLIB uf20-91 benchmark. Parallel tempering improves success probability on 332 instances while worsening only 5. Crucially, these gains are concentrated on hard instances where independent solvers fail. Violation trajectory analysis confirms the underlying mechanism: temperature exchanges allow replicas to traverse energy barriers unreachable by fixed-temperature dynamics, successfully escaping the narrow basins that constrain the baseline. To our knowledge, this represents the first integration of parallel tempering into an SNN-based CSP solver.

cs.ET↗

arXiv2026

Implicitly Parallel Neuromorphic Solver Design for Constraint Satisfaction Problems

Many real-life problems of practical importance -- spanning a wide range of applications from chip design to bioinformatics -- represent constraint satisfaction problems, where classical solvers have to rely on heuristic approximations due to the computational complexity. Neuromorphic solvers, on the other hand, offer a unique alternative representation which enables an inherently parallel exploration of the solution space. This paper provides a theoretical characterization and experimental demonstration of this native type of parallelism that is hard to apply to classical solvers. We observe that more than two orders of magnitude faster operation is possible without compromising solution accuracy. Our study represents the first step toward bridging the theory vs. practice gap to unlock the performance potential of emerging neuromorphic solvers.

cs.ET↗

arXiv2026

An FPGA-ASIC Co-Design Framework for Capacity-Constrained Physics-Based Ising Chips

When a problem exceeds an analog Ising machine's spin capacity it cannot be solved in one shot: a digital orchestration layer must iteratively decompose the graph, clamp boundary spins, and deliver hardware-sized subproblems to the solver. As per-subproblem solve times reach the us-scale regime, this digital layer (not the analog core) becomes the primary scalability bottleneck. On a 28 nm CMOS coupled-oscillator Ising chip (T_core ~ 77.5 us, 24 mW), a CPU orchestrator leaves the solver idle for over 98% of every iteration at N=750, and the gap survives OpenMP and AVX2 optimization because it is dominated by data-dependent memory access rather than arithmetic throughput. We argue that the orchestration layer is a first-class design object and propose a sizing methodology for hybrid analog-digital Ising systems: given a solver's core time, clock frequency, and target problem class, it gives an analytical baseline for hardware parallelism and memory-bandwidth dimensioning. Guided by the sizing laws, an FPGA orchestration layer co-located with the chip satisfies the pipeline condition with substantial margin. Across graph coloring, MaxCut, and SAT benchmarks it delivers 9.8x-46.5x raw end-to-end time-to-solution (TTS) improvements (14.8x-65.9x on per-repeat runtime) over the optimized CPU orchestrator, with device-level power reductions of 85x-116x.

cs.ET↗

arXiv2026

Extractive summarization on a CMOS Ising machine

Extractive summarization (ES) aims to generate a concise summary by selecting a subset of sentences from a document while maximizing relevance and minimizing redundancy. Although modern ES systems achieve high accuracy using powerful neural models, their deployment typically relies on CPU or GPU infrastructures that are energy-intensive and poorly suited for real-time inference in resource-constrained environments. In this work, we explore the feasibility of implementing McDonald-style extractive summarization on a low-power CMOS coupled oscillator-based Ising machine (COBI) that supports integer-valued, all-to-all spin couplings. We first propose a hardware-aware Ising formulation that reduces the scale imbalance between local fields and coupling terms, thereby improving robustness to coefficient quantization: this method can be applied to any problem formulation that requires k of n variables to be chosen. We then develop a complete ES pipeline including (i) stochastic rounding and iterative refinement to compensate for precision loss, and (ii) a decomposition strategy that partitions a large ES problem into smaller Ising subproblems that can be efficiently solved on COBI and later combined. Experimental results on the CNN/DailyMail dataset show that our pipeline can produce high-quality summaries using only integer-coupled Ising hardware with limited precision. COBI achieves 3-4.5x runtime speedups compared to a brute-force method, which is comparable to software Tabu search, and two to three orders of magnitude reductions in energy, while maintaining competitive summary quality. These results highlight the potential of deploying CMOS Ising solvers for real-time, low-energy text summarization on edge devices.

cs.LG↗

arXiv2025

On Solving Structured SAT on Ising Machines: A Semiprime Factorization Study

Ising machines are emerging as a new technology for solving various classes of computationally hard problems of practical importance, yet their limits on structured SAT workloads, representative of numerous real-world applications, remain unexplored. We present the first systematic study of such problems, using semiprime factorization as a representative case. Our results show that highly restrictive, 'tight' constraints, when mapped into optimization form, fundamentally distort Ising dynamics, and that these distortions are amplified when problems are decomposed to fit within limited hardware. We propose a hybrid approach that offloads constraint-heavy components to classical preprocessing while reserving the computationally challenging part for the Ising machine. Structured SAT represents a crucial step toward real-world applications, which remain out of reach today due to Ising machine limitations. Our findings reveal that constraint handling is a central obstacle and highlight hybrid hardware-software approaches as the path forward to unlocking the long-term potential of Ising machines. We conduct our evaluation on the manufactured Ising chips and demonstrate that our flow more than doubles the solvable problem size on a 45-spin all-to-all Ising chip, from 8-bit (94 variables) to 11-bit (190 variables), without hardware changes.

cs.ET↗

arXiv2025

Supporting Higher-Order Interactions in Practical Ising Machines

Ising machines as hardware solvers of combinatorial optimization problems (COPs) can efficiently explore large solution spaces due to their inherent parallelism and physics-based dynamics. Many important COP classes such as satisfiability (SAT) assume arbitrary interactions between problem variables, while most Ising machines only support pairwise (second-order) interactions. This necessitates translation of higher-order interactions to pair-wise, which typically results in extra variables not corresponding to problem variables, and a larger problem for the Ising machine to solve than the original problem. This in turn can significantly increase time-to-solution and/or degrade solution accuracy. In this paper, considering a representative CMOS-compatible class of Ising machines, we propose a practical design to enable direct hardware support for higher order interactions. By minimizing the overhead of problem translation and mapping, our design leads to up to 4x lower time-to-solution without compromising solution accuracy.

physics.comp-ph↗

arXiv2024

HETRI: Heterogeneous Ising Multiprocessing

Ising machines are effective solvers for complex combinatorial optimization problems. The idea is mapping the optimal solution(s) to a combinatorial optimization problem to the minimum energy state(s) of a physical system, which naturally converges to a minimum energy state upon perturbance. The underlying mathematical abstraction, the Ising model, can capture the dynamic behavior of different physical systems by mapping each problem variable to a spin which can interact with other spins. Ising model as a mathematical abstraction can be mapped to hardware using traditional devices. In this paper we instead focus on Ising machines which represent a network of physical spins directly implemented in hardware using, e.g., quantum bits or electronic oscillators. To eliminate the scalability bottleneck due to the mismatch in problem vs. Ising machine size and connectivity, in this paper we make the case for HETRI: Heterogeneous Ising Multiprocessing. HETRI organizes the maximum number of physical spins that the underlying technology supports in Ising cores; and multiple independent Ising cores, in Ising chips. Ising cores in a chip feature different inter-spin connectivity or spin counts to match the problem characteristics. We provide a detailed design space exploration and quantify the performance in terms of time or energy to solution and solution accuracy with respect to homogeneous alternatives under the very same hardware budget and considering the very same spin technology.

cs.ET↗