arXiv subjects

Alex Pappachen James

Publications and source records attributed to Alex Pappachen James.

At least 37 records · Page 2Linked to original sources

arXiv2018

Implementation of Chua's chaotic oscillator with an HP memristor

This paper proposes an innovative chaotic circuit based on Chua's oscillator. It combines traditional realization of a non-linear resistor in Chua's chaotic oscillator with a promising memristive circuitry. This mixed implementation connects old research works that were focused on diodes with relatively new research papers that are, now, concentrated on memristors. As a result, more reliable chaotic circuit with an HP memristor is obtained that could be used as a source of randomness. Dynamic behavior of the circuit is studied by obtaining fft analysis, different chaotic attractors and Lyapunov exponent spectrum. The results show that the addition of a memristor enhances chaotic behavior of the circuit while maintaining the same power dissipation.

cs.ET↗

arXiv2018

Memristor-based Approximation of Gaussian Filter

A Gaussian filter is a filter with impulse response of Gaussian function. These filters are useful in image processing of 2D signals, as it removes unnecessary noise. Also, they could be helpful for data transmission (e.g. GMSK modulation). In practice, the Gaussian filters could be approximately designed by several methods. One of these methods are to construct Gaussian-like filter with the help of memristors and RLC circuits. Therefore, the objective of this project is to find and design appropriate model of Gaussian-like filter, by using mentioned devices. Finally, one possible model of Gaussian-like filter based on memristor designed and analysed in this paper.

eess.SP↗

arXiv2018

Hierarchical Temporal Memory using Memristor Networks: A Survey

This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state of the art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions are provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations and unreliability of the memristive devices integrated with CMOS circuits are also discussed.

cs.AR↗

arXiv2018

Feature extraction without learning in an analog Spatial Pooler memristive-CMOS circuit design of Hierarchical Temporal Memory

Hierarchical Temporal Memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.

cs.ET↗

arXiv2018

Neuron inspired data encoding memristive multi-level memory cell

Mapping neuro-inspired algorithms to sensor backplanes of on-chip hardware require shifting the signal processing from digital to the analog domain, demanding memory technologies beyond conventional CMOS binary storage units. Using memristors for building analog data storage is one of the promising approaches amongst emerging non-volatile memory technologies. Recently, a memristive multi-level memory (MLM) cell for storing discrete analog values has been developed in which memory system is implemented combining memristors in voltage divider configuration. In given example, the memory cell of 3 sub-cells with a memristor in each was programmed to store ternary bits which overall achieved 10 and 27 discrete voltage levels. However, for further use of proposed memory cell in analog signal processing circuits data encoder is required to generate control voltages for programming memristors to store discrete analog values. In this paper, we present the design and performance analysis of data encoder that generates write pattern signals for 10 level memristive memory.

cs.ET↗

arXiv2018

Level-Shifted Neural Encoded Analog-to-Digital Converter

This paper presents the new approach in implementation of analog-to-digital converter (ADC) that is based on Hopfield neural-network architecture. Hopfield neural ADC (NADC) is a type of recurrent neural network that is effective in solving simple optimization problems, such as analog-to-digital conversion. The main idea behind the proposed design is to use multiple 2-bit Hopfield NADCs operating as quantizers in parallel, where analog input signal to each successive 2-bit Hopfield ADC block is passed through a voltage level shifter. This is followed by a neural network encoder to remove the quantization errors. In traditional Hopfield NADC based designs, increasing the number of bits could require proper scaling of the network parameters, in particular digital output operating region. Furthermore, the resolution improvement of traditional Hopfield NADC creates digital error that increases with the increasing number of bits. The proposed design is scalable in number of bits and number of quantization levels, and can maintain the magnitude of digital output code within a manageable operating voltage range.

cs.ET↗

arXiv2018

Facial emotion recognition using min-max similarity classifier

Recognition of human emotions from the imaging templates is useful in a wide variety of human-computer interaction and intelligent systems applications. However, the automatic recognition of facial expressions using image template matching techniques suffer from the natural variability with facial features and recording conditions. In spite of the progress achieved in facial emotion recognition in recent years, the effective and computationally simple feature selection and classification technique for emotion recognition is still an open problem. In this paper, we propose an efficient and straightforward facial emotion recognition algorithm to reduce the problem of inter-class pixel mismatch during classification. The proposed method includes the application of pixel normalization to remove intensity offsets followed-up with a Min-Max metric in a nearest neighbor classifier that is capable of suppressing feature outliers. The results indicate an improvement of recognition performance from 92.85% to 98.57% for the proposed Min-Max classification method when tested on JAFFE database. The proposed emotion recognition technique outperforms the existing template matching methods.

cs.CV↗

arXiv2018

Quality assessment metrics for edge detection and edge-aware filtering: A tutorial review

The quality assessment of edges in an image is an important topic as it helps to benchmark the performance of edge detectors, and edge-aware filters that are used in a wide range of image processing tasks. The most popular image quality metrics such as Mean squared error (MSE), Peak signal-to-noise ratio (PSNR) and Structural similarity (SSIM) metrics for assessing and justifying the quality of edges. However, they do not address the structural and functional accuracy of edges in images with a wide range of natural variabilities. In this review, we provide an overview of all the most relevant performance metrics that can be used to benchmark the quality performance of edges in images. We identify four major groups of metrics and also provide a critical insight into the evaluation protocol and governing equations.

cs.CV↗

arXiv2018

Automated image segmentation for detecting cell spreading for metastasizing assessments of cancer development

The automated segmentation of cells in microscopic images is an open research problem that has important implications for studies of the developmental and cancer processes based on in vitro models. In this paper, we present the approach for segmentation of the DIC images of cultured cells using G-neighbor smoothing followed by Kauwahara filtering and local standard deviation approach for boundary detection. NIH FIJI/ImageJ tools are used to create the ground truth dataset. The results of this work indicate that detection of cell boundaries using segmentation approach even in the case of realistic measurement conditions is a challenging problem.

cs.CV↗

arXiv2017

Neuromorphic adaptive edge-preserving denoising filter

In this paper, we present on-sensor neuromorphic vision hardware implementation of denoising spatial filter. The mean or median spatial filters with fixed window shape are known for its denoising ability, however, have the drawback of blurring the object edges. The effect of blurring increases with an increase in window size. To preserve the edge information, we propose an adaptive spatial filter that uses neuron's ability to detect similar pixels and calculates the mean. The analog input differences of neighborhood pixels are converted to the chain of pulses with voltage controlled oscillator and applied as neuron input. When the input pulses charge the neuron to equal or greater level than its threshold, the neuron will fire, and pixels are identified as similar. The sequence of the neuron's responses for pixels is stored in the serial-in-parallel-out shift register. The outputs of shift registers are used as input to the selector switches of an averaging circuit making this an adaptive mean operation resulting in an edge preserving mean filter. System level simulation of the hardware is conducted using 150 images from Caltech database with added Gaussian noise to test the robustness of edge-preserving and denoising ability of the proposed filter. Threshold values of the hardware neuron were adjusted so that the proposed edge-preserving spatial filter achieves optimal performance in terms of PSNR and MSE, and these results outperforms that of the conventional mean and median filters.

eess.IV↗

arXiv2017

On-chip Face Recognition System Design with Memristive Hierarchical Temporal Memory

Hierarchical Temporal Memory is a new machine learning algorithm intended to mimic the working principle of neocortex, part of the human brain, which is responsible for learning, classification, and making predictions. Although many works illustrate its effectiveness as a software algorithm, hardware design for HTM remains an open research problem. Hence, this work proposes an architecture for HTM Spatial Pooler and Temporal Memory with learning mechanism, which creates a single image for each class based on important and unimportant features of all images in the training set. In turn, the reduction in the number of templates within database reduces the memory requirements and increases the processing speed. Moreover, face recognition analysis indicates that for a large number of training images, the proposed design provides higher accuracy results (83.5\%) compared to only Spatial Pooler design presented in the previous works.

cs.ET↗

arXiv2017

Memristive System Design for Variable Pixel G-Neighbor Denoising Filter

Image blurring artifact is the main challenge to any spatial, denoising filters. This artifact is contributed by the heterogeneous intensities within the given neighborhood or window of fixed size. Selection of most similar intensities (G-Neighbors) helps to adapt the window shape which is of edge-aware nature and subsequently reduce this blurring artifact. The paper presents a memristive circuit design to implement this variable pixel G-Neighbor filter. The memristive circuits exhibits parallel processing capabilities (near real-time) and neuromorphic architectures. The proposed design is demonstrated as simulations of both algorithm (MATLAB) and circuit (SPICE). Circuit design is evaluated for various parameters such as processing time, fabrication area used, and power consumption. Denoising performance is demonstrated using image quality metrics such as peak signal-to-noise ratio (PSNR), mean square error (MSE), and structural similarity index measure (SSIM). Combining adaptive filtering method with mean filter resulted in average improvement of MSE to about 65\% reduction, increase of PSNR and SSIM to nearly 18\% and 12\% correspondingly.

cs.ET↗

arXiv2017

Multi-level Memristive Memory with Resistive Networks

Analog memory is of great importance in neurocomputing technologies field, but still remains difficult to implement. With emergence of memristors in VLSI technologies the idea of designing scalable analog data storage elements finds its second wind. A memristor, known for its history dependent resistance levels, independently can provide blocks of binary or discrete state data storage. However, using single memristor to save the analog value is practically limited due to the device variability and implementation complexity. In this paper, we present a new design of discrete state memory cell consisting of subcells constructed from a memristor and its resistive network. A memristor in the sub-cells provides the storage element, while its resistive network is used for programming its resistance. Several sub-cells are then connected in parallel, resembling potential divider configuration. The output of the memory cell is the voltage resulting from distributing the input voltage among the sub-cells. Here, proposed design was programmed to obtain 10 and 27 different output levels depending on the configuration of the combined resistive networks within the sub-cell. Despite the simplicity of the circuit, this realization of multilevel memory provides increased number of output levels compared to previous designs of memory technologies based on memristors. Simulation results of proposed memory are analyzed providing explicit data on the issues of distinguishing discrete analog output levels and sensitivity of the cell to oscillations in write signal patterns.

cs.ET↗

arXiv2017

High Voltage Insulator Surface Evaluation Using Image Processing

High voltage insulators are widely deployed in power systems to isolate the live- and dead-part of overhead lines as well as to support the power line conductors mechanically. Permanent, secure and safe operation of power transmission lines require that the high voltage insulators are inspected and monitor, regularly. Severe environment conditions will influence insulator surface and change creepage distance. Consequently, power utilities and transmission companies face significant problem in operation due to insulator damage or contamination. In this study, a new technique is developed for real-time inspection of insulator and estimating the snow, ice and water over the insulator surface which can be a potential risk of operation breakdown. To examine the proposed system, practical experiment is conducted using ceramic insulator for capturing the images with snow, ice and wet surface conditions. Gabor and Standard deviation filters are utilized for image feature extraction. The best achieved recognition accuracy rate was 87% using statistical approach the Standard deviation.

cs.CV↗

arXiv2016

Memristor Threshold Logic: An Overview to Challenges and Applications

Once referred to as the missing circuit component, memristor has come long way across to be recognized and taken as important to future circuit designs. The memristor due to its ability to memorize the state, switch between different resistance level, smaller size and low leakage currents makes it useful for a wide range of intelligent memory and computing applications. This overview paper highlights broadly provides the uses of memristor in the implementation of cognitive cells for different imaging and pattern matching applications.

cs.ET↗

arXiv2016

CMOS-Memristor Hybrid Integrated Pixel Sensors

Increase in image resolution require the ability of image sensors to pack an increased number of circuit components in a given area. On the the other hand a high speed processing of signals from the sensors require the ability of pixel to carry out pixel parallel operations. In the paper, we propose a modified 3T and 4T CMOS wide dynamic range pixels, which we refer as 2T-M and 3T-M configurations, comprising of MOSFETS and memristors. The low leakage currents and low area of memristors helps to achieve the objective of reducing the area, while the possibility to create arrays of memristors and MOSFETs across different layers within the chip, ensure the possibility to scale the circuit architecture.

cs.ET↗

arXiv2016

Voltage Controlled Memristor Threshold Logic Gates

In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show that in comparison with CMOS-only logic, the proposed system shows significant improvements in terms of device area, power dissipation and leakage power.

cs.ET↗

arXiv2016

CMOS-Memristor Dendrite Threshold Circuits

Non-linear neuron models overcomes the limitations of linear binary models of neurons that have the inability to compute linearly non-separable functions such as XOR. While several biologically plausible models based on dendrite thresholds are reported in the previous studies, the hardware implementation of such non-linear neuron models remain as an open problem. In this paper, we propose a circuit design for implementing logical dendrite non-linearity response of dendrite spike and saturation types. The proposed dendrite cells are used to build XOR circuit and intensity detection circuit that consists of different combinations of dendrite cells with saturating and spiking responses. The dendrite cells are designed using a set of memristors, Zener diodes, and CMOS NOT gates. The circuits are designed, analyzed and verified on circuit boards.

cs.ET↗