arXiv subjects

Andrea Padovani

Publications and source records attributed to Andrea Padovani.

5 recordsLinked to original sources

arXiv2026

System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability

Complementary FETs (CFETs) extend nanosheet FET (NSFET) scaling by vertically stacking n- and p-type gate-all-around (GAA) devices, thereby shrinking standard-cell area. The performance gain, however, cannot be assessed from device metrics alone, as CFET layouts also introduce larger cell-level parasitic resistance and capacitance (RC). In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in A7 CFET and A10 NSFET technology nodes. Our flow links calibrated device models, optimized standard-cell generation, automated GDS-to-TCAD conversion enabling accurate 3D parasitic RC extraction, full RTL-to-GDS implementation for an AI accelerator, multiphysics thermal analysis, and physics-based bias temperature instability (BTI) aging evaluation. Using the same device model for both technologies, we can isolate the impact of parasitic RCs and design at different levels of the design flow. The results of the AI accelerator design demonstrate that the A7 CFET reduces the chip area by 24.7% and the total wire length by 12%, improving the area efficiency TOPS/mm^2 by 74% relative to the baseline of the A10 NSFET. Under iso-frequency operation, results reveal that CFET voltage scaling reduces power by 68% and lowers power density from 148 W/cm^2 to 55 W/cm^2, which reduces the chip's temperature from 125 degrees C down to merely 62 degrees C. The resulting reduction in stress temperature suppresses 10-year BTI-induced degradation by 39%, reducing the required aging timing guardband by 53%.

cs.ET↗

arXiv2026

Defect-Aware Physics-Based Compact Model for Ferroelectric nvCap: From TCAD Calibration to Circuit Co-Design

Ferroelectric non-volatile capacitance-based memories enable non-destructive readout and low-power in-memory computing with 3D stacking potential. However, their limited memory window (1-10 fF/μm) requires material-device-circuit co-optimization. Existing compact models fail to capture the physics of small-signal capacitance, device variability, and cycling degradation, which are critical parameters for circuit design. In non-volatile capacitance devices, the small-signal capacitance difference of the polarization states is the key metric. The majority of the reported compact models do not incorporate any physical model of the capacitance as a function of voltage and polarization. We present a physics-based compact model that captures small-signal capacitance, interface and bulk defect contributions, and device variations through multi-scale modeling combining experimental data, TCAD simulations, and circuit validation. Based on this methodology, we show optimized memory read-out with +/- 5 mV sense margin and impact of device endurance at the circuit level. This work presents a comprehensive compact model which enables the design of selector-less arrays and 3D-stacked memories for compute-in-memory and storage memory.

cs.ET↗

arXiv2026

Engineering Wake-Up-Free Ferroelectric Capacitors with Enhanced High-Temperature Reliability

We systematically explore the design space of ferroelectric hafnium-zirconium oxide (H0.5Z0.5O or HZO) heterostructures for reliable high temperature operation. HZO films are deposited using thermal and plasma-enhanced atomic layer deposition (Th-ALD and PE-ALD) on tungsten (W) and titanium nitride (TiN) bottom electrodes (BE), while maintaining identical top electrodes. We demonstrate that PE-ALD HZO capacitors integrated with W BE exhibit wake-up-free switching up to 125C, along with significantly improved endurance compared to Th-ALD HZO/W devices across a wide temperature range (85-125C). By decoupling the contributions of the plasma-deposited HZO film and the oxidized bottom interface inherently formed during PE-ALD, we identify the oxidized W interfacial layer (WOx) as the primary factor governing endurance enhancement and wake-up suppression at elevated temperatures, while the PE-ALD HZO film provides secondary benefits in reducing wake-up. In contrast, PE-ALD HZO capacitors fabricated on TiN BE show no substantial improvement in wake-up behavior or endurance relative to Th-ALD HZO/TiN devices, despite the formation of an unintentional TiOxNy interfacial layer, and instead exhibit degraded polarization. This difference arises from the significantly weaker endurance enhancement and no wake-up suppression provided by oxidized TiN compared to oxidized W under comparable oxidation conditions. Overall, PE-ALD HZO films enable superior ferroelectric performance at elevated temperatures only when deposited on W BE, while Th-ALD HZO films remain a viable option for high temperature operation on TiN BE. These findings clarify the interplay between deposition technique, electrode chemistry, and interfacial oxidation, and provide design guidelines for integrating ferroelectric memories into monolithic 3D systems under stringent thermal constraints.

cond-mat.mtrl-sci↗

arXiv2026

ALD-Derived WO3-x Leads to Nearly Wake-Up-Free Ferroelectric Hf0.5Zr0.5O2 at Elevated Temperatures

Breaking the memory wall in advanced computing architectures will require complex 3D integration of emerging memory materials such as ferroelectrics-either within the back-end-of-line (BEOL) of CMOS front-end processes or through advanced 3D packaging technologies. Achieving this integration demands that memory materials exhibit high thermal resilience, with the capability to operate reliably at elevated temperatures such as 125C, due to the substantial heat generated by front-end transistors. However, silicon-compatible HfO2-based ferroelectrics tend to exhibit antiferroelectric-like behavior in this temperature range, accompanied by a more pronounced wake-up effect, posing significant challenges to their thermal reliability. Here, we report that by introducing a thin tungsten oxide (WO3-x) layer-known as an oxygen reservoir-and carefully tuning its oxygen content, ultra-thin Hf0.5Zr0.5O2 (5 nm) films can be made robust against the ferroelectric-to-antiferroelectric transition at elevated temperatures. This approach not only minimizes polarization loss in the pristine state but also effectively suppresses the wake-up effect, reducing the required wake-up cycles from 105 to only 10 at 125C- a qualifying temperature for back-end memory integrated with front-end logic, as defined by the JEDEC standard. First-principles density functional theory calculations reveal that WO3 enhances the stability of the ferroelectric orthorhombic phase at elevated temperatures by increasing the tetragonal-to-orthorhombic phase energy gap, and promoting favorable phonon mode evolution, thereby supporting o-phase formation under both thermodynamic and kinetic constraints.

cond-mat.mtrl-sci↗

arXiv2025

A Dual-Memory Ferroelectric Transistor Emulating Synaptic Metaplasticity for High-Speed Reservoir Computing

The exponential growth of edge artificial intelligence demands material-focused solutions to overcome energy consumption and latency limitations when processing real-time temporal data. Physical reservoir computing (PRC) offers an energy-efficient paradigm but faces challenges due to limited device scalability and reconfigurability. Additionally, reservoir and readout layers require memory of different timescales, short-term and long-term respectively - a material challenge hindering CMOS-compatible implementations. This work demonstrates a CMOS-compatible ferroelectric transistor using hafnium-zirconium-oxide (HZO) and silicon, enabling dual-memory operation. This system exhibits non-volatile long-term memory (LTM) from ferroelectric HZO polarization and volatile short-term memory (STM) from engineered non-quasi-static (NQS) channel-charge relaxation driven by gate-source/drain overlap capacitance. Ferroelectric polarization acts as non-volatile programming of volatile dynamics: by modulating threshold voltage, the ferroelectric state deterministically switches the NQS time constant and computational behavior between paired-pulse facilitation (PPF) and depression (PPD). This establishes a generalizable material-design principle applicable to diverse ferroelectric-semiconductor heterostructures, extending beyond silicon to oxide semiconductors and heterogeneously-integrated systems. The device solves second-order nonlinear tasks with 3.69 x 10^-3 normalized error using only 16 reservoir states - ~5x reduction - achieving 20 us response time (~1000x faster) and 1.5 x 10^-7 J energy consumption, providing an immediately manufacturable pathway for neuromorphic hardware and energy-efficient edge intelligence.

cond-mat.other↗