arXiv subjects

Andreas Tsiamis

Publications and source records attributed to Andreas Tsiamis.

3 recordsLinked to original sources

arXiv2026

Parallel Spatial Photonic Programming of Optoelectronic IGZO RRAM with a compact $\mu$LED Array

Optoelectronic resistive random-access memory elements (ORRAM) are critical emerging devices that leverage photonic technologies to bring the advantages of optical programming to traditionally electronic memristive platforms for neuromorphic computing and artificial intelligence. In this work, a free-space optic micro-LED ($\mu$LED) array is combined with a 2-terminal oxide semiconductor ORRAM (based on IGZO\textsubscript{Rich}/IGZO active layers), to realise parallel spatial programming of form-free memristive arrays. We report the optical and electrical programming of resistive states with potentiation/depression analysis of various stimuli parameters (pulse frequency, pulse width, pulse amplitude). Further, we demonstrate the simultaneous photonic-electronic programming of the ORRAM with optical SET (blue 450\,nm) and electrical RESET functionality. Persistent photocurrent is also observed and exploited as a pathway to fading memory or synaptic plasticity for temporal bit encoding. Finally, parallel optical $\mu$LED to ORRAM channels are demonstrated to achieve the simultaneous photonic programming of multiple devices and the writing of spatial patterns across a chip of memristive IGZO devices. This work highlights the light-enabled scalability of the optoelectronic platform and the feasibility of ORRAM to interface with spatially-multiplexed optical sources to bring neuromorphic technologies directly into applications that process and sense in the optical domain.

physics.optics↗

arXiv2025

A Rapid-prototyping CMOS-RRAM Integration Strategy

Moore's law has long served the semiconductor industry as the driving force for producing ever-advancing electronics technologies. However, given the economic implications and technological challenges associated with the present semiconductor scaling constraints, a shift from a traditional more Moore approach to a beyond Moore paradigm is desirable for sustaining the current pace of innovation beyond the established development route. Resistive random-access memories (RRAM) are one such beyond Moore technology that offers many avenues for innovation, and when integrated with mature complementary metal oxide semiconductors (CMOS), can extend CMOS capabilities in a scalable and power-efficient manner, both in terms of memory and computation. Nevertheless, as emerging and established technologies fuse, existing semiconductor-optimised manufacturing faces significant challenges, while the methodologies and complexities of integration are often not highlighted in depth, or overlooked at the expense of demonstrating the application-specific integrated-technologies. In this article, we focus on the integration, and detail a cost-effective, rapid-prototyping, and technology agnostic CMOS-RRAM integration strategy that employs hybridised wafer-level and multi-reticle processing techniques, supported by a systematic increased complexity approach. Leveraging the fact that CMOS technologies can be readily realised by taking advantage of mature front-end-of-line fabrication processes offered by semiconductor foundries, we establish an in-house RRAM development program that allows to combine fundamental material and device-level knowledge with custom-designed CMOS electronics. This approach utilises fully CMOS-compatible and transferable processes, ultimately enabling a seamless transition from research and development to volume production.

cond-mat.mtrl-sci↗

arXiv2025

Multibit Ferroelectric Memcapacitor for Non-volatile Analogue Memory and Reconfigurable Filtering

Tuneable capacitors are vital for adaptive and reconfigurable electronics, yet existing approaches require continuous bias or mechanical actuation. Here we demonstrate a voltage-programmable ferroelectric memcapacitor based on HfZrO that achieves more than eight stable, reprogrammable capacitance states (3-bit encoding) within a non-volatile window of 24~pF. The device switches at low voltages (3~V), with each state exhibiting long retention (10^5~s) and high endurance (10^6 cycles), ensuring reliable multi-level operation. At the nanoscale, multistate charge retention was directly visualised using atomic force microscopy, confirming the robustness of individual states beyond macroscopic measurements. As a proof of concept, the capacitor was integrated into a high-pass filter, where the programmed capacitive states shift the cutoff frequency over 5~kHz, establishing circuit-level viability. This work demonstrates the feasibility of CMOS-compatible, non-volatile, analogue memory based on ferroelectric HfZrO, paving the way for adaptive RF filters, reconfigurable analogue front-ends, and neuromorphic electronics.

cond-mat.mtrl-sci↗