A Rapid-prototyping CMOS-RRAM Integration Strategy

Abstract

Moore's law has long served the semiconductor industry as the driving force for producing ever-advancing electronics technologies. However, given the economic implications and technological challenges associated with the present semiconductor scaling constraints, a shift from a traditional more Moore approach to a beyond Moore paradigm is desirable for sustaining the current pace of innovation beyond the established development route. Resistive random-access memories (RRAM) are one such beyond Moore technology that offers many avenues for innovation, and when integrated with mature complementary metal oxide semiconductors (CMOS), can extend CMOS capabilities in a scalable and power-efficient manner, both in terms of memory and computation. Nevertheless, as emerging and established technologies fuse, existing semiconductor-optimised manufacturing faces significant challenges, while the methodologies and complexities of integration are often not highlighted in depth, or overlooked at the expense of demonstrating the application-specific integrated-technologies. In this article, we focus on the integration, and detail a cost-effective, rapid-prototyping, and technology agnostic CMOS-RRAM integration strategy that employs hybridised wafer-level and multi-reticle processing techniques, supported by a systematic increased complexity approach. Leveraging the fact that CMOS technologies can be readily realised by taking advantage of mature front-end-of-line fabrication processes offered by semiconductor foundries, we establish an in-house RRAM development program that allows to combine fundamental material and device-level knowledge with custom-designed CMOS electronics. This approach utilises fully CMOS-compatible and transferable processes, ultimately enabling a seamless transition from research and development to volume production.