arXiv subjects

Anup Joshi

Publications and source records attributed to Anup Joshi.

5 recordsLinked to original sources

arXiv2026

Impedance-Based Sensitivity Analysis for Stability Enhancement of LCC-HVDC Links Connected to Weak Grids Using Grid-Forming Converters

This paper presents a frequency-domain, impedance-based sensitivity methodology for stability assessment and enhancement of line-commutated converter HVDC (LCC-HVDC) links operating under weak-grid conditions. The methodology integrates frequency-domain identification tailored for black-box systems, the Generalized Nyquist Criterion (GNC) for multivariable stability assessment, and modal impedance decomposition with participation-factor analysis to locate and interpret interaction mechanisms. The approach is validated against a detailed linearized state-space model and nonlinear EMT simulations of an LCC-HVDC benchmark. A sensitivity study varying the grid short-circuit ratio (SCR) reveals a stability limit for the standalone LCC-HVDC link and demonstrates that the integration of a grid-forming voltage source converter (GFM-VSC) substantially increases the stability margin.

eess.SY↗

arXiv2026

Sizing of a grid-forming power converter to improve the small-signal stability of an LCC-HVDC system connected to a weak grid

Line-commutated converter high-voltage direct current (LCC-HVDC) has proven to be a reliable technology for bulk power transmission over long distances. However, the growing penetration of converter interfaced generation (CIG) is resulting in weaker AC grids, rendering the operation of LCC-HVDC systems vulnerable and posing a serious challenge to their stability. Grid-forming (GFM) controlled voltage source converter (VSC) have been shown to provide stabilizing impact in weak grid conditions. However, the impact of GFM controlled VSCs (GFM-VSC) on stability of LCC-HVDC in weak grid conditions has not been studied in depth in the literature. In this paper, a simplified model of LCC-HVDC is proposed and validated. Then a small-signal state-space model of a system consisting of aforementioned LCC-HVDC, a GFM-VSC and an infinite grid is developed to study the interactions between different components. The small-signal stability analysis shows the stabilizing effect of the GFM-VSC on the stability of the LCC-HVDC link in weak grid condition. Furthermore, the study on the sizing of the GFM power converter reveals that even a modest share of the capacity of the GFM power converter relative to the total nominal apparent power (sum of nominal power of LCC-HVDC and the nominal apparent power of GFM-VSC) is sufficient to ensure the stability of the system, in the test system analyzed in this study. This work just focuses in small-signal stability, but it is important to highlight that other stability phenomena should also be taken into account when selecting the final size of the GFM-VSC.

eess.SY↗

arXiv2023

Constant RMR Recoverable Mutex under System-wide Crashes

We design two Recoverable Mutual Exclusion (RME) locks for the system-wide crash model. Our first algorithm requires only $O(1)$ space per process, and achieves $O(1)$ worst-case RMR complexity in the CC model. Our second algorithm enhances the first algorithm to achieve (the same) $O(1)$ space per process and $O(1)$ worst-case RMR complexity in both the CC and DSM models. Furthermore, both algorithms allow dynamically created threads of arbitrary names to join the protocol and access the locks. To our knowledge, these are the only RME locks to achieve worst-case $O(1)$ RMR complexity assuming nothing more than standard hardware support. In light of Chan and Woelfel's $\Omega(\log n / \log\log n)$ worst-case RMR lower bound for RME in the individual crash model, our results show a separation between the system-wide crash and individual crash models in worst-case RMR complexity in both the CC and DSM models.

cs.DC↗

arXiv2020

Recoverable Mutual Exclusion with Abortability

Recent advances in non-volatile main memory (NVRAM) technology have spurred research on designing algorithms that are resilient to process crashes. This paper is a fuller version of our conference paper \cite{jayanti:rmeabort}, which presents the first Recoverable Mutual Exclusion (RME) algorithm that supports abortability. Our algorithm uses only the read, write, and CAS operations, which are commonly supported by multiprocessors. It satisfies FCFS and other standard properties. Our algorithm is also adaptive. On DSM and Relaxed-CC multiprocessors, a process incurs $O(\min(k, \log n))$ RMRs in a passage and $O(f+ \min(k, \log n))$ RMRs in an attempt, where $n$ is the number of processes that the algorithm is designed for, $k$ is the point contention of the passage or the attempt, and $f$ is the number of times that $p$ crashes during the attempt. On a Strict CC multiprocessor, the passage and attempt complexities are $O(n)$ and $O(f+n)$. Attiya et al. proved that, with any mutual exclusion algorithm, a process incurs at least $\Omega(\log n)$ RMRs in a passage, if the algorithm uses only the read, write, and CAS operations \cite{Attiya:lbound}. This lower bound implies that the worst-case RMR complexity of our algorithm is optimal for the DSM and Relaxed CC multiprocessors.

cs.DC↗

arXiv2019

A Recoverable Mutex Algorithm with Sub-logarithmic RMR on Both CC and DSM

In light of recent advances in non-volatile main memory technology, Golab and Ramaraju reformulated the traditional mutex problem into the novel {\em Recoverable Mutual Exclusion} (RME) problem. In the best known solution for RME, due to Golab and Hendler from PODC 2017, a process incurs at most $O(\frac{\log n}{\log \log n})$ remote memory references (RMRs) per passage, where a passage is an interval from when a process enters the Try section to when it subsequently returns to Remainder. Their algorithm, however, guarantees this bound only for cache-coherent (CC) multiprocessors, leaving open the question of whether a similar bound is possible for distributed shared memory (DSM) multiprocessors. We answer this question affirmatively by designing an algorithm that satisfies the same complexity bound as Golab and Hendler's for both CC and DSM multiprocessors. Our algorithm has some additional advantages over Golab and Hendler's: (i) its Exit section is wait-free, (ii) it uses only the Fetch-and-Store instruction, and (iii) on a CC machine our algorithm needs each process to have a cache of only $O(1)$ words, while their algorithm needs $O(n)$ words.

cs.DC↗