arXiv subjects

Azad Naeemi

Publications and source records attributed to Azad Naeemi.

At least 19 recordsLinked to original sources

arXiv2026

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

We propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO$_2$/ZrO$_2$/HfO$_2$ (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology. A novel neighbor-cell shared source/drain (S/D) bitline (BL) design enlarges the IGO contact area to mitigate contact resistance and restore PG drive without area penalty. The resulting cell achieves a 25\% footprint reduction vs the high-performance (HP) 122 Si baseline while maintaining robust static noise margin (SNM) over a wide supply voltage range. At the 128$\times$256 subarray-level, it reduces write delay by 42.2\% and EDP by 9.7\% compared to the high-density (HD) 111 Si baseline, owing to reduced cell parasitics and wordline (WL) loading from the smaller footprint.

cs.AR↗

arXiv2025

Modeling and Optimization of Two-Terminal Spin-Orbit-Torque MRAM

This paper presents physical modeling and benchmarking for two-terminal spin-orbit torque magnetic random-access memory (2T-SOT-MRAM). The results indicate that the common SOT materials that provide only in-plane torque can provide little to no improvement over spin-transfer-torque (STT) MRAM in terms of write energy. However, emerging SOT materials that provide out-of-plane torques with efficiencies as small as 0.1 can result in significant improvements in the write energy for such 2-terminal devices, especially when the magnet lateral dimensions are scaled down to 30 or 20 nm. Additionally, a novel 2T-SOT MRAM device is proposed that can increase the path electrons pass through the SOT layer; hence, increasing the generated spin current and the energy efficiency of the device. Our benchmarking results indicate that an out-of-plane SOT efficiency of 0.051 for 20nm wide devices can result in write energies approaching SRAM at the 7nm technology node.

cond-mat.mes-hall↗

arXiv2025

Content Addressable Memory Design with Reference Resistor for Improved Search Resolution

Despite the parallel in-memory search capabilities of content addressable memories (CAMs), their use in applications is constrained by their limited resolution that worsens as they are scaled to larger arrays or advanced nodes. In this work we present experimental results for a novel back-end-of-line compatible reference resistive device that can significantly improve the search resolution of CAMs implemented with CMOS and beyond-CMOS technologies to less than or equal to 5-bits.

cs.ET↗

arXiv2024

A 5T-2MTJ STT-assisted Spin Orbit Torque based Ternary Content Addressable Memory for Hardware Accelerators

In this work, we present a novel non-volatile spin transfer torque (STT) assisted spin-orbit torque (SOT) based ternary content addressable memory (TCAM) with 5 transistors and 2 magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device-level to application-level. At the device-level, various write characteristics such as write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bitcells while also accounting for the impact of interconnect parasitics at the 7nm technology node. A search error rate of 3.9x10^-11 is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.

cs.ET↗

arXiv2024

Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search

In this paper we present a comprehensive design and benchmarking study of Content Addressable Memory (CAM) at the 7nm technology node in the context of similarity search applications. We design CAM cells based on SRAM, spin-orbit torque, and ferroelectric field effect transistor devices and from their layouts extract cell parasitics using state of the art EDA tools. These parasitics are used to develop SPICE netlists to model search operations. We use a CAM-based dataset search and a sequential recommendation system to highlight the application-level performance degradation due to interconnect parasitics. We propose and evaluate two solutions to mitigate interconnect effects.

cs.ET↗

arXiv2022

Quantum Games and Interactive Tools for Quantum Technologies Outreach and Education

In this article, we provide an extensive overview of a wide range of quantum games and interactive tools that have been employed by the community in recent years. The paper presents selected tools, as described by their developers. The list includes Hello Quantum, Hello Qiskit, Particle in a Box, Psi and Delta, QPlayLearn, Virtual Lab by Quantum Flytrap, Quantum Odyssey, ScienceAtHome, and The Virtual Quantum Optics Laboratory. Additionally, we present events for quantum game development: hackathons, game jams, and semester projects. Furthermore, we discuss the Quantum Technologies Education for Everyone (QUTE4E) pilot project, which illustrates an effective integration of these interactive tools with quantum outreach and education activities. Finally, we aim at providing guidelines for incorporating quantum games and interactive tools in pedagogic materials to make quantum technologies more accessible for a wider population.

physics.ed-ph↗

arXiv2021

Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits

Spintronic devices are a promising beyond-CMOS device option thanks to their energy efficiency and compatibility with CMOS. To accurately capture their multi-physics dynamics, a rigorous treatment of both spin and charge and their inter-conversion is required. Here we present physics-based device models based on 4x4 matrices for the spin-orbit coupling part of the magneto-electric spin-orbit (MESO) device. Also, a more rigorous physics model of ferroelectric and magnetoelectric switching of ferromagnets, based on Landau-Lifshitz-Gilbert (LLG) and Landau-Khalatnikov (LK) equations, is presented. With the combined model implemented in a SPICE circuit simulator environment, simulation results were obtained which show feasibility of MESO implementation and functional operation of buffers, oscillators, and majority gates.

cond-mat.mes-hall↗

arXiv2020

Physical Mechanism behind the Hysteresis-free Negative Capacitance Effect in Metal-Ferroelectric-Insulator-Metal Capacitors with Dielectric Leakage and Interfacial Trapped Charges

The negative capacitance (NC) stabilization of a ferroelectric (FE) material can potentially provide an alternative way to further reduce the power consumption in ultra-scaled devices and thus has been of great interest in technology and science in the past decade. In this article, we present a physical picture for a better understanding of the hysteresis-free charge boost effect observed experimentally in metal-ferroelectric-insulator-metal (MFIM) capacitors. By introducing the dielectric (DE) leakage and interfacial trapped charges, our simulations of the hysteresis loops are in a strong agreement with the experimental measurements, suggesting the existence of an interfacial oxide layer at the FE-metal interface in metal-ferroelectric-metal (MFM) capacitors. Based on the pulse switching measurements, we find that the charge enhancement and hysteresis are dominated by the FE domain viscosity and DE leakage, respectively. Our simulation results show that the underlying mechanisms for the observed hysteresis-free charge enhancement in MFIM may be physically different from the alleged NC stabilization and capacitance matching. Moreover, the link between Merz's law and the phenomenological kinetic coefficient is discussed, and the possible cause of the residual charges observed after pulse switching is explained by the trapped charge dynamics at the FE-DE interface. The physical interpretation presented in this work can provide important insights into the NC effect in MFIM capacitors and future studies of low-power logic devices.

physics.app-ph↗

arXiv2020

A micromagnetic study of the switching dynamics of the BiFeO$_3$/CoFe heterojunction

The switching dynamics of a single-domain BiFeO3/CoFe heterojunction is modeled and key parameters such as interface exchange coupling coefficient are extracted from experimental results. The lower limit of the magnetic order response time of CoFe in the BiFeO3/CoFe heterojunction is theoretically quantified to be on to the order of 100 ps. Our results indicate that the switching behavior of CoFe in the BiFeO3/CoFe heterojunction is dominated by the rotation of the Neel vector in BiFeO3 rather than the unidirectional exchange bias at the interface. We also quantify the magnitude of the interface exchange coupling coefficient J_int to be 0.32 pJ/m by comparing our simulation results with the giant magnetoresistance (GMR) curves and the magnetic hysteresis loop in the experiments. To the best of our knowledge, this is the first time that J_int is extracted quantitatively from experiments. Furthermore, we demonstrate that the switching success rate and the thermal stability of the BiFeO3/CoFe heterojunction can be improved by reducing the thickness of CoFe and increasing the length to width aspect ratio of the BiFeO3/CoFe heterojunction. Our theoretical model provides a comprehensive framework to study the magnetoelectric properties and the manipulation of the magnetic order of CoFe in the BiFeO3/CoFe heterojunction.

cond-mat.mtrl-sci↗

arXiv2020

Materials Requirements of High-Speed and Low-Power Spin-Orbit-Torque Magnetic Random-Access Memory

As spin-orbit-torque magnetic random-access memory (SOT-MRAM) is gathering great interest as the next-generation low-power and high-speed on-chip cache memory applications, it is critical to analyze the magnetic tunnel junction (MTJ) properties needed to achieve sub-ns, and ~fJ write operation when integrated with CMOS access transistors. In this paper, a 2T-1MTJ cell-level modeling framework for in-plane type Y SOT-MRAM suggests that high spin Hall conductivity and moderate SOT material sheet resistance are preferred. We benchmark write energy and speed performances of type Y SOT cells based on various SOT materials experimentally reported in the literature, including heavy metals, topological insulators and semimetals. We then carry out detailed benchmarking of SOT material Pt, beta-W, and BixSe(1-x) with different thickness and resistivity. We further discuss how our 2T-1MTJ model can be expanded to analyze other variations of SOT-MRAM, including perpendicular (type Z) and type X SOT-MRAM, two-terminal SOT-MRAM, as well as spin-transfer-torque (STT) and voltage-controlled magnetic anisotropy (VCMA)-assisted SOT-MRAM. This work will provide essential guidelines for SOT-MRAM materials, devices, and circuits research in the future.

physics.app-ph↗

arXiv2019

Bipolar electric field switching of perpendicular magnetic tunnel junctions through voltage controlled exchange coupling

Perpendicular magnetic tunnel junctions (p-MTJs) switched utilizing bipolar electric fields have extensive applications in energy-efficient memory and logic devices. Voltage-controlled magnetic anisotropy linearly lowers the energy barrier of ferromagnetic layer via electric field effect and efficiently switches p-MTJs only with a unipolar behavior. Here we demonstrate a bipolar electric field effect switching of 100-nm p-MTJs with a synthetic antiferromagnetic free layer through voltage-controlled exchange coupling (VCEC). The switching current density, ~1.1x10^5 A/cm^2, is one order of magnitude lower than that of the best-reported spin-transfer torque devices. Theoretical results suggest that electric field induces a ferromagnetic-antiferromagnetic exchange coupling transition of the synthetic antiferromagnetic free layer and generates a field-like interlayer exchange coupling torque, which cause the bidirectional magnetization switching of p-MTJs. A preliminary benchmarking simulation estimates that VCEC dissipates an order of magnitude lower writing energy compared to spin-transfer torque at the 15-nm technology node. These results could eliminate the major obstacle in the development of spin memory devices beyond their embedded applications.

physics.app-ph↗

arXiv2019

Multi-domain Characterization of Ferroelectric Switching Dynamics with a Physics-based SPICE Circuit Model for Phase Field Simulations

In this paper, the multi-domain nature of ferroelectric (FE) polarization switching dynamics in a metal-ferroelectric-metal (MFM) capacitor is explored through a physics-based phase field approach, where the three-dimensional time-dependent Ginzburg-Landau (TDGL) equation and Poisson's equation are self-consistently solved with the SPICE simulator. Systematically calibrated based on the experimental measurements, the model well captures transient negative capacitance in pulse switching dynamics, with domain interaction and viscosity being the key parameters. It is found that the influence of pulse amplitudes on voltage transient behaviors can be attributed to the fact that the FE free energy profile strongly depends on how the domains are interacted. This finding has an important implication on the charge-boost induced by stabilization of negative capacitance in an FE + dielectric (DE) stack since the so-called capacitance matching needs to be designed at a specific operation voltage or frequency. In addition, we extract the domain viscosity dynamics during polarization switching according to the experimental measurements. For the first time, a physics-based circuit-compatible SPICE model for multi-domain phase field simulations is established to reveal the effect of domain interaction on the FE energy profile and microscopic domain evolution.

physics.app-ph↗

arXiv2019

Simulation of the Magnetization Dynamics of a Single Domain BiFeO$_3$ Thin Film

The switching dynamics of a single-domain BiFeO$_3$ thin films is investigated through combining the dynamics of polarization and Neel vector. The evolution of the ferroelectric polarization is described by the Landau-Khalatnikov (LK) equation, and the Landau-Lifshitz-Gilbert (LLG) equations for spins in two sublattices to model the time evolution of the antiferromagnetic order (Neel vector) in a G-type antiferromagnet. This work theoretically demonstrates that due to the rotation of the magnetic hard axis following the polarization reversal, the Neel vector can be switched by 180 degrees, while the weak magnetization can remain unchanged. The simulation results are consistent with the ab initio calculation, where the Neel vector rotates during polarization rotation, and also match our calculation of the dynamics of order parameter using Landau-Ginzburg theory. We also find that the switching time of the Neel vector is determined by the speed polarization switching and is predicted to be as short as 30 ps.

cond-mat.mes-hall↗

arXiv2018

A mixed signal architecture for convolutional neural networks

Deep neural network (DNN) accelerators with improved energy and delay are desirable for meeting the requirements of hardware targeted for IoT and edge computing systems. Convolutional neural networks (CoNNs) belong to one of the most popular types of DNN architectures. This paper presents the design and evaluation of an accelerator for CoNNs. The system-level architecture is based on mixed-signal, cellular neural networks (CeNNs). Specifically, we present (i) the implementation of different layers, including convolution, ReLU, and pooling, in a CoNN using CeNN, (ii) modified CoNN structures with CeNN-friendly layers to reduce computational overheads typically associated with a CoNN, (iii) a mixed-signal CeNN architecture that performs CoNN computations in the analog and mixed signal domain, and (iv) design space exploration that identifies what CeNN-based algorithm and architectural features fare best compared to existing algorithms and architectures when evaluated over common datasets -- MNIST and CIFAR-10. Notably, the proposed approach can lead to 8.7$\times$ improvements in energy-delay product (EDP) per digit classification for the MNIST dataset at iso-accuracy when compared with the state-of-the-art DNN engine, while our approach could offer 4.3$\times$ improvements in EDP when compared to other network implementations for the CIFAR-10 dataset.

cs.CV↗

arXiv2018

Hybrid Piezoelectric-Magnetic Neurons: A Proposal for Energy-Efficient Machine Learning

This paper proposes a spintronic neuron structure composed of a heterostructure of magnets and a piezoelectric with a magnetic tunnel junction (MTJ). The operation of the device is simulated using SPICE models. Simulation results illustrate that the energy dissipation of the proposed neuron compared to that of other spintronic neurons exhibits 70% improvement. Compared to CMOS neurons, the proposed neuron occupies a smaller footprint area and operates using less energy. Owing to its versatility and low-energy operation, the proposed neuron is a promising candidate to be adopted in artificial neural network (ANN) systems.

physics.app-ph↗

arXiv2018

Skyrmion nucleation via localized spin current injection in confined nanowire geometry in low chirality magnetic materials

Magnetic skyrmions have been the focus of intense research with promising applications in memory, logic and interconnect technology. Several schemes have been recently proposed and demonstrated to nucleate skyrmions. However, they either result in an uncontrolled skyrmion bubble production or are mostly targeted towards integration with racetrack memory device. In this work, we propose a novel scheme for a controlled single skyrmion nucleation in a confined nanowire geometry with sub-100 nm width using a generalized approach of "localized spin current injection" technique in material systems exhibiting low Dzyaloshinskii-Moriya interaction (DMI). Our proposed nucleation mechanism follows a pathway involving the creation of a reversed magnetic domain containing one or more pairs of vertical Bloch lines (VBLs) that form an edge-to-edge domain wall as the VBLs get annihilated at the edge of the nanowire. However, pinning of the edge domain walls within a narrow gap using notches or anti-notches results in the creation of a magnetic bubble with defect-free domain wall that eventually relaxes into a circular skyrmion structure. Our simulations predict that the proposed mechanism allows skyrmion nucleation on sub-nanosecond timescale, shows robustness to variations like local pinning sites and is applicable for any skyrmion-based logic, memory and interconnect application.

cond-mat.mes-hall↗

arXiv2017

Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation

We propose a heterostructure device comprised of magnets and piezoelectrics that significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low voltage operation, non-reciprocity, non-volatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21x shorter delay and 27x lower energy dissipation per bit for a 32-bit arithmetic-logic unit (ALU).

physics.app-ph↗

arXiv2017

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 {\mu}m$^2$ for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

physics.app-ph↗