arXiv subjects

Bing Li

Publications and source records attributed to Bing Li.

At least 469 records · Page 26Linked to original sources

arXiv2017

On Timing Model Extraction and Hierarchical Statistical Timing Analysis

In this paper, we investigate the challenges to apply Statistical Static Timing Analysis (SSTA) in hierarchical design flow, where modules supplied by IP vendors are used to hide design details for IP protection and to reduce the complexity of design and verification. For the three basic circuit types, combinational, flip-flop-based and latch-controlled, we propose methods to extract timing models which contain interfacing as well as compressed internal constraints. Using these compact timing models the runtime of full-chip timing analysis can be reduced, while circuit details from IP vendors are not exposed. We also propose a method to reconstruct the correlation between modules during full-chip timing analysis. This correlation can not be incorporated into timing models because it depends on the layout of the corresponding modules in the chip. In addition, we investigate how to apply the extracted timing models with the reconstructed correlation to evaluate the performance of the complete design. Experiments demonstrate that using the extracted timing models and reconstructed correlation full-chip timing analysis can be several times faster than applying the flattened circuit directly, while the accuracy of statistical timing analysis is still well maintained.

cs.AR↗

arXiv2017

ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing

Length-matching is an important technique to bal- ance delays of bus signals in high-performance PCB routing. Existing routers, however, may generate very dense meander segments. Signals propagating along these meander segments exhibit a speedup effect due to crosstalk between the segments of the same wire, thus leading to mismatch of arrival times even under the same physical wire length. In this paper, we present a post-processing method to enlarge the width and the distance of meander segments and hence distribute them more evenly on the board so that crosstalk can be reduced. In the proposed framework, we model the sharing of available routing areas after removing dense meander segments from the initial routing, as well as the generation of relaxed meander segments and their groups for wire length compensation. This model is transformed into an ILP problem and solved for a balanced distribution of wire patterns. In addition, we adjust the locations of long wire segments according to wire priorities to swap free spaces toward critical wires that need much length compensation. To reduce the problem space of the ILP model, we also introduce a progressive fixing technique so that wire patterns are grown gradually from the edge of the routing toward the center area. Experimental results show that the proposed method can expand meander segments significantly even under very tight area constraints, so that the speedup effect can be alleviated effectively in high- performance PCB designs.

cs.AR↗

arXiv2017

Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements

Post-silicon clock tuning elements are widely used in high-performance designs to mitigate the effects of process variations and aging. Located on clock paths to flip-flops, these tuning elements can be configured through the scan chain so that clock skews to these flip-flops can be adjusted after man- ufacturing. Owing to the delay compensation across consecutive register stages enabled by the clock tuning elements, higher yield and enhanced robustness can be achieved. These benefits are, nonetheless, attained by increasing die area due to the inserted clock tuning elements. For balancing performance improvement and area cost, an efficient timing analysis algorithm is needed to evaluate the performance of such a circuit. So far this evaluation is only possible by Monte Carlo simulation which is very timing- consuming. In this paper, we propose an alternative method using graph transformation, which computes a parametric minimum clock period and is more than 10 4 times faster than Monte Carlo simulation while maintaining a good accuracy. This method also identifies the gates that are critical to circuit performance, so that a fast analysis-optimization flow becomes possible.

cs.AR↗

arXiv2017

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning

At submicron manufacturing technology nodes, pro- cess variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin to maintain yield, leading to an unaffordable overdesign. Most of these margins, however, are wasted after manufacturing, because process variations cause only some chips to be really slow, while other chips can easily meet given timing specifications. To reduce this pessimism, we can reserve less timing margin and tune failed chips after manufacturing with clock buffers to make them meet timing specifications. With this post-silicon clock tuning, critical paths can be balanced with neighboring paths in each chip specifically to counter the effect of process variations. Consequently, chips with timing failures can be rescued and the yield can thus be improved. This is specially useful in high- performance designs, e.g., high-end CPUs, where clock binning makes chips with higher performance much more profitable. In this paper, we propose a method to determine where to insert post-silicon tuning buffers during the design phase to improve the overall profit with clock binning. This method learns the buffer locations with a Sobol sequence iteratively and reduces the buffer ranges afterwards with tuning concentration and buffer grouping. Experimental results demonstrate that the proposed method can achieve a profit improvement of about 14% on average and up to 26%, with only a small number of tuning buffers inserted into the circuit.

cs.AR↗

arXiv2017

Timing Model Extraction for Sequential Circuits Considering Process Variations

As semiconductor devices continue to scale down, process vari- ations become more relevant for circuit design. Facing such variations, statistical static timing analysis is introduced to model variations more accurately so that the pessimism in tra- ditional worst case timing analysis is reduced. Because all de- lays are modeled using correlated random variables, most statis- tical timing methods are much slower than corner based timing analysis. To speed up statistical timing analysis, we propose a method to extract timing models for flip-flop and latch based sequential circuits respectively. When such a circuit is used as a module in a hierarchical design, the timing model instead of the original circuit is used for timing analysis. The extracted timing models are much smaller than the original circuits. Ex- periments show that using extracted timing models accelerates timing verification by orders of magnitude compared to previ- ous approaches using flat netlists directly. Accuracy is main- tained, however, with the mean and standard deviation of the clock period both showing usually less than 1% error compared to Monte Carlo simulation on a number of benchmark circuits.

cs.AR↗

arXiv2017

EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers

At nanometer manufacturing technology nodes, process variations significantly affect circuit performance. To combat them, post- silicon clock tuning buffers can be deployed to balance timing bud- gets of critical paths for each individual chip after manufacturing. The challenge of this method is that path delays should be mea- sured for each chip to configure the tuning buffers properly. Current methods for this delay measurement rely on path-wise frequency stepping. This strategy, however, requires too much time from ex- pensive testers. In this paper, we propose an efficient delay test framework (EffiTest) to solve the post-silicon testing problem by aligning path delays using the already-existing tuning buffers in the circuit. In addition, we only test representative paths and the delays of other paths are estimated by statistical delay prediction. Exper- imental results demonstrate that the proposed method can reduce the number of frequency stepping iterations by more than 94% with only a slight yield loss.

cs.AR↗

arXiv2017

Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.

cs.ET↗

arXiv2017

PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model

In static timing analysis, clock-to-q delays of flip-flops are considered as constants. Setup times and hold times are characterized separately and also used as constants. The characterized delays, setup times and hold times, are ap- plied in timing analysis independently to verify the perfor- mance of circuits. In reality, however, clock-to-q delays of flip-flops depend on both setup and hold times. Instead of being constants, these delays change with respect to different setup/hold time combinations. Consequently, the simple ab- straction of setup/hold times and constant clock-to-q delays introduces inaccuracy in timing analysis. In this paper, we propose a holistic method to consider the relation between clock-to-q delays and setup/hold time combinations with a piecewise linear model. The result is more accurate than that of traditional timing analysis, and the incorporation of the interdependency between clock-to-q delays, setup times and hold times may also improve circuit performance.

cs.AR↗

arXiv2017

Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability

At submicron manufacturing technology nodes process variations affect circuit performance significantly. This trend leads to a large timing margin and thus overdesign to maintain yield. To combat this pessimism, post-silicon clock tuning buffers can be inserted into circuits to balance timing budgets of critical paths with their neighbors. After manufacturing, these clock buffers can be configured for each chip individually so that chips with timing failures may be rescued to improve yield. In this paper, we propose a sampling-based method to determine the proper locations of these buffers. The goal of this buffer insertion is to reduce the number of buffers and their ranges, while still maintaining a good yield improvement. Experimental results demonstrate that our algorithm can achieve a significant yield improvement (up to 35%) with only a small number of buffers.

cs.AR↗

arXiv2017

Static Timing Model Extraction for Combinational Circuits

For large circuits, static timing analysis (STA) needs to be performed in a hierarchical manner to achieve higher performance in arrival time propagation. In hierarchical STA, efficient and accurate timing models of sub-modules need to be created. We propose a timing model extraction method that significantly reduces the size of timing models without losing any accuracy by removing redundant timing information. Circuit components which do not contribute to the delay of any input to output pair are removed. The proposed method is deterministic. Compared to the original models, the numbers of edges and vertices of the resulting timing models are reduced by 84% and 85% on average, respectively, which are significantly more than the results achieved by other methods.

cs.AR↗

arXiv2017

Comment on "Observation of the Wigner-Huntington transition to metallic hydrogen"

Dias and Silvera (Letters, p. 715, 2017) claim the observation of the Wigner-Huntington transition to metallic hydrogen at 495 GPa. We show that neither the claims of the record pressure or the phase transition to a metallic state are supported by any data and contradict the authors' own unconfirmed previous results.

cond-mat.mtrl-sci↗

arXiv2017

The existence and global exponential stability of almost periodic solutions for neutral type CNNs on time scales

In this paper, a class of neutral type competitive neural networks with mixed time-varying delays and leakage delays on time scales is proposed. Based on the exponential dichotomy of linear dynamic equations on time scales, Banach's fixed point theorem and the theory of calculus on time scales, some sufficient conditions that are independent of the backwards graininess function of the time scale are obtained for the existence and global exponential stability of almost periodic solutions for this class of neural networks. The obtained results are completely new and indicate that both the continuous time and the discrete time cases of the networks share the same dynamical behavior. Finally, an examples is given to show the effectiveness of the obtained results.

math.CA↗

arXiv2017

The exceptional sets on the run-length function of beta-expansions

Let $β> 1$ and the run-length function $r_n(x,β)$ be the maximal length of consecutive zeros amongst the first n digits in the $β$-expansion of $x\in[0,1]$. The exceptional set $$E_{\max}^φ=\left\{x \in [0,1]:\liminf_{n\rightarrow \infty}\frac{r_n(x,β)}{φ(n)}=0, \limsup_{n\rightarrow \infty}\frac{r_n(x,β)}{φ(n)}=+\infty\right\}$$ is investigated, where $φ: \mathbb{N} \rightarrow \mathbb{R}^+$ is a monotonically increasing function with $\lim\limits_{n\rightarrow \infty }φ(n)=+\infty$. We prove that the set $E_{\max}^φ$ is either empty or of full Hausdorff dimension and residual in $[0,1]$ according to the increasing rate of $φ$ .

math.DS↗

arXiv2017

Genericity of dimension drop on self-affine sets

We prove that generically, for a self-affine set in $\mathbb{R}^d$, removing one of the affine maps which defines the set results in a strict reduction of the Hausdorff dimension. This gives a partial positive answer to a folklore open question.

math.DS↗

arXiv2016

TDSelector: A Training Data Selection Method for Cross-Project Defect Prediction

In recent years, cross-project defect prediction (CPDP) attracted much attention and has been validated as a feasible way to address the problem of local data sparsity in newly created or inactive software projects. Unfortunately, the performance of CPDP is usually poor, and low quality training data selection has been regarded as a major obstacle to achieving better prediction results. To the best of our knowledge, most of existing approaches related to this topic are only based on instance similarity. Therefore, the objective of this work is to propose an improved training data selection method for CPDP that considers both similarity and the number of defects each training instance has (denoted by defects), which is referred to as TDSelector, and to demonstrate the effectiveness of the proposed method. Our experiments were conducted on 14 projects (including 15 data sets) collected from two public repositories. The results indicate that, in a specific CPDP scenario, the TDSelector-based bug predictor performs, on average, better than those based on the baseline methods, and the AUC (area under ROC curve) values are increased by up to 10.6 and 4.3%, respectively. Besides, an additional experiment shows that selecting those instances with more bugs directly as training data can further improve the performance of the bug predictor trained by our method.

cs.SE↗

arXiv2016

The topological property of the irregular sets on the lengths of basic intervals in beta-expansions

Let $β> 1$ be a real number and $(ε_1(x, β), ε_2(x, β), \ldots)$ be the $β$-expansion of a point $x \in (0, 1]$. For all $x \in (0,1]$, let $A(D(x))$ be the set of accumulation points of $\frac{-\log_β|I_n(x)|}{n}$ as $n \rightarrow \infty$, where $|I_n(x)|$ is the length of the basic interval of order $n$ containing $x \in (0, 1]$. In this paper, we prove that $A(D(x))$ is always a closed interval for any $x \in (0,1]$. Furthermore, if $λ(β)>0$, the extremely irregular set containing points $x \in [0, 1]$ whose upper limit of $\frac{-\log_β|I_n(x)|}{n}$ equals to $1+ł(β)$ is residual, where $1+ł(β)$ is a constant depending on $β$. As a consequence, the irregular set with $x\in [0, 1]$ whose limit of $\frac{-\log_β|I_n(x)|}{n}$ does not exist is residual for every $λ(β)>0$.

math.DS↗

arXiv2016

Rotor-phonon coupling in perovskite CH3NH3PbI3: the origin of exceptional transport properties

Atomic dynamics takes a fundamental part in numbers of physical properties of solids like high-Tc superconductivity, semiconducting transports, and thermoelectricity. Perovskite CH3NH3PbI3 exhibits outstanding photovoltaic performances, but the exact physical scenario has not been established yet, due to the inadequate understanding of the atomic dynamics and exceptional transport properties. We present a complete atomic dynamic picture consisting of phonons, rotational modes of protons and molecular vibrational modes, which is constructed by carrying out high-resolution time-of-flight inelastic neutron scattering measurements in a wide energy window ranging from 0.0036 to 54 meV on a large single crystal sample. A three-fold rotational mode of protons activated around 80 K reduces the lifetimes of acoustic and optical phonons down to about 4.5 ps and below 1 ps at 150 K, respectively. The orthorhombic to tetragonal phase transition takes place with a slower four-fold rotational mode of the C-N axis concomitantly setting in at ~ 165 K, above which the optical phonons are too broadened to be distinguished whereas the acoustic ones are still robust. The significantly reduced lifetimes of optical phonons are linked to the smaller mobility of charge carriers while the ultralow lattice thermal conductivity is attributed to nanoscale mean free paths of acoustic phonons. These microscopic insights provide a solid standing point, on which perovskite solar cells can be understood more accurately and their performances are perhaps further optimized. The revealed rotor-phonon coupling opens up an emergent opportunity to create unprecedented functionalities of materials.

cond-mat.mtrl-sci↗

arXiv2016

The dimension of irregular set in parameter space

For any real number $β>1$. The $n$th cylinder of $β$ in the parameter space $\{β\in \mathbb{R}: β>1\}$ is a set of real numbers in $(1,\infty)$ having the same first $n$ digits in their $β$-expansion of $1$, denote by $I^P_n(β)$. We study the quantities which describe the growth of the length of $I^P_n(β)$. The Huasdorff dimension of the set of given growth rate of the length of $I^P_n(β)$ will be determined in this paper.

math.DS↗