arXiv subjects

Carl Grace

Publications and source records attributed to Carl Grace.

5 recordsLinked to original sources

arXiv2026

Machine Learning on Heterogeneous, Edge, and Quantum Hardware for Particle Physics (ML-HEQUPP)

The next generation of particle physics experiments will face a new era of challenges in data acquisition, due to unprecedented data rates and volumes along with extreme environments and operational constraints. Harnessing this data for scientific discovery demands real-time inference and decision-making, intelligent data reduction, and efficient processing architectures beyond current capabilities. Crucial to the success of this experimental paradigm are several emerging technologies, such as artificial intelligence and machine learning (AI/ML), silicon microelectronics, and the advent of quantum algorithms and processing. Their intersection includes areas of research such as low-power and low-latency devices for edge computing, heterogeneous accelerator systems, reconfigurable hardware, novel codesign and synthesis strategies, readout for cryogenic or high-radiation environments, and analog computing. This white paper presents a community-driven vision to identify and prioritize research and development opportunities in hardware-based ML systems and corresponding physics applications, contributing towards a successful transition to the new data frontier of fundamental science.

physics.ins-det↗

arXiv2024

Investigating Resource-efficient Neutron/Gamma Classification ML Models Targeting eFPGAs

There has been considerable interest and resulting progress in implementing machine learning (ML) models in hardware over the last several years from the particle and nuclear physics communities. A big driver has been the release of the Python package, hls4ml, which has enabled porting models specified and trained using Python ML libraries to register transfer level (RTL) code. So far, the primary end targets have been commercial FPGAs or synthesized custom blocks on ASICs. However, recent developments in open-source embedded FPGA (eFPGA) frameworks now provide an alternate, more flexible pathway for implementing ML models in hardware. These customized eFPGA fabrics can be integrated as part of an overall chip design. In general, the decision between a fully custom, eFPGA, or commercial FPGA ML implementation will depend on the details of the end-use application. In this work, we explored the parameter space for eFPGA implementations of fully-connected neural network (fcNN) and boosted decision tree (BDT) models using the task of neutron/gamma classification with a specific focus on resource efficiency. We used data collected using an AmBe sealed source incident on Stilbene, which was optically coupled to an OnSemi J-series SiPM to generate training and test data for this study. We investigated relevant input features and the effects of bit-resolution and sampling rate as well as trade-offs in hyperparameters for both ML architectures while tracking total resource usage. The performance metric used to track model performance was the calculated neutron efficiency at a gamma leakage of 10$^{-3}$. The results of the study will be used to aid the specification of an eFPGA fabric, which will be integrated as part of a test chip.

cs.LG↗

arXiv2022

Big Industry Engagement to Benefit HEP: Microelectronics Support from Large CAD Companies

Microelectronics development is critical to a wide number of DOE projects and mission space. Creating Helpful Incentives to Produce Semiconductors (CHIPS) and manufacturing Application Specific Integrated Circuits (ASIC) are important to DOE, so the infrastructure that allows DOE to carry out its mission needs to exist. This paper discusses the current initiatives and recommends a business model to build an ecosystem for microelectronics design for DOE which includes three main building blocks: the Computer Aided Design (CAD) - Electronic Design Automation (EDA) design tools, basic design IPs, and access to semiconductor fabrication facilities.

physics.soc-ph↗

arXiv2022

Monolithic Active Pixel Sensors on CMOS technologies

Collider detectors have taken advantage of the resolution and accuracy of silicon detectors for at least four decades. Future colliders will need large areas of silicon sensors for low mass trackers and sampling calorimetry. Monolithic Active Pixel Sensors (MAPS), in which Si diodes and readout circuitry are combined in the same pixels, and can be fabricated in some of standard CMOS processes, are a promising technology for high-granularity and light detectors. In this paper we review 1) the requirements on MAPS for trackers and electromagnetic calorimeters (ECal) at future colliders experiments, 2) the ongoing efforts towards dedicated MAPS for the Electron-Ion Collider (EIC) at BNL, for which the EIC Silicon Consortium was already instantiated, and 3) space-born applications for MeV $\gamma$-ray experiments with MAPS based trackers (AstroPix).

physics.ins-det↗

arXiv2020

Cryogenic Characterization of 180 nm CMOS Technology at 100 mK

Conventional CMOS technology operated at cryogenic conditions has recently attracted interest for its uses in low-noise electronics. We present one of the first characterizations of 180 nm CMOS technology at a temperature of 100 mK, extracting I/V characteristics, threshold voltages, and transconductance values, as well as observing their temperature dependence. We find that CMOS devices remain fully operational down to these temperatures, although we observe hysteresis effects in some devices. The measurements described in this paper can be used to inform the future design of CMOS devices intended to be operated in this deep cryogenic regime.

physics.ins-det↗