arXiv subjects

Chao Luo

Publications and source records attributed to Chao Luo.

At least 19 recordsLinked to original sources

arXiv2026

IKFST: IOO and KOO Algorithms for Accelerated and Precise WFST-based End-to-End Automatic Speech Recognition

End-to-end automatic speech recognition has become the dominant paradigm in both academia and industry. To enhance recognition performance, the Weighted Finite-State Transducer (WFST) is widely adopted to integrate acoustic and language models through static graph composition, providing robust decoding and effective error correction. However, WFST decoding relies on a frame-by-frame autoregressive search over CTC posterior probabilities, which severely limits inference efficiency. Motivated by establishing a more principled compatibility between WFST decoding and CTC modeling, we systematically study the two fundamental components of CTC outputs, namely blank and non-blank frames, and identify a key insight: blank frames primarily encode positional information, while non-blank frames carry semantic content. Building on this observation, we introduce Keep-Only-One and Insert-Only-One, two decoding algorithms that explicitly exploit the structural roles of blank and non-blank frames to achieve significantly faster WFST-based inference without compromising recognition accuracy. Experiments on large-scale in-house, AISHELL-1, and LibriSpeech datasets demonstrate state-of-the-art recognition accuracy with substantially reduced decoding latency, enabling truly efficient and high-performance WFST decoding in modern speech recognition systems.

cs.SD↗

arXiv2025

Enhancing Agentic RL with Progressive Reward Shaping and Value-based Sampling Policy Optimization

Large Language Models (LLMs) empowered with Tool-Integrated Reasoning (TIR) can iteratively plan, call external tools, and integrate returned information to solve complex, long-horizon reasoning tasks. Agentic Reinforcement Learning (Agentic RL) optimizes such models over full tool-interaction trajectories, but two key challenges hinder effectiveness: (1) Sparse, non-instructive rewards, such as binary 0-1 verifiable signals, provide limited guidance for intermediate steps and slow convergence; (2) Gradient degradation in Group Relative Policy Optimization (GRPO), where identical rewards within a rollout group yield zero advantage, which reducing sample efficiency. To address these challenges, we propose two complementary techniques: Progressive Reward Shaping (PRS) and Value-based Sampling Policy Optimization (VSPO). PRS is a curriculum-inspired reward design that introduces dense, stage-wise feedback - encouraging models to first master parseable and properly formatted tool calls, then optimize for factual correctness and answer quality. We instantiate PRS for short-form QA (with a length-aware BLEU to fairly score concise answers) and long-form QA (with LLM-as-a-Judge scoring to prevent reward hacking). VSPO is an enhanced GRPO variant that replaces zero advantages samples with prompts selected by a task-value metric balancing difficulty and uncertainty, and applies value-smoothing clipping to stabilize gradient updates. Experiments on multiple short-form and long-form QA benchmarks show that PRS consistently outperforms traditional binary rewards, and VSPO achieves superior stability, faster convergence, and higher final performance compared to SFT, PPO and GRPO baselines. Together, PRS and VSPO yield LLM-based TIR agents that generalize better across domains.

cs.CL↗

arXiv2025

Teaching LLM to be Persuasive: Reward-Enhanced Policy Optimization for Alignment from Heterogeneous Rewards

We deploy large language models (LLMs) as business development (BD) agents for persuasive price negotiation in online travel agencies (OTAs). The agent must follow a multi-stage Standard Operating Procedure (SOP) and strict guardrails (no over-promising and no hallucinations), while remaining human-like and effective over long, multi-turn dialogues. We propose Reward-Enhanced Policy Optimization (REPO), a reinforcement learning post-training method that combines heterogeneous rewards: a preference-trained reward model (RM), an LLM-as-a-judge (RJ) for nuanced behaviors (e.g., emotional value and SOP compliance), and rule-based reward functions (RF) (mainly regex-based) for deterministic checks on numerics, formatting, and guardrails. In expert consensus evaluation (three human experts; 30 online conversations and 45 curated bad cases), REPO improves average dialogue rating to 4.63 (+0.33 over GRPO) and raises the share of conversations with at least one excellent response to 66.67% (+23.34 pp over GRPO), while achieving a 93.33% bad-case fix rate with 75.56% clean fixes. In a production A/B test on 9,653 real customer conversations (vs. an intent-driven dialogue system), REPO improves response rate by +12.14 pp and task success rate by +5.94 pp (p<0.001).

cs.CL↗

arXiv2025

Breaking Through the Spike: Spike Window Decoding for Accelerated and Precise Automatic Speech Recognition

Recently, end-to-end automatic speech recognition has become the mainstream approach in both industry and academia. To optimize system performance in specific scenarios, the Weighted Finite-State Transducer (WFST) is extensively used to integrate acoustic and language models, leveraging its capacity to implicitly fuse language models within static graphs, thereby ensuring robust recognition while also facilitating rapid error correction. However, WFST necessitates a frame-by-frame search of CTC posterior probabilities through autoregression, which significantly hampers inference speed. In this work, we thoroughly investigate the spike property of CTC outputs and further propose the conjecture that adjacent frames to non-blank spikes carry semantic information beneficial to the model. Building on this, we propose the Spike Window Decoding algorithm, which greatly improves the inference speed by making the number of frames decoded in WFST linearly related to the number of spiking frames in the CTC output, while guaranteeing the recognition performance. Our method achieves SOTA recognition accuracy with significantly accelerates decoding speed, proven across both AISHELL-1 and large-scale In-House datasets, establishing a pioneering approach for integrating CTC output with WFST.

eess.AS↗

arXiv2023

Characterization and Modeling of Silicon-on-Insulator Lateral Bipolar Junction Transistors at Liquid Helium Temperature

Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain ($\beta$). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on-insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates $\beta$ degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current ($\textit{I}_\textbf{C}$) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

physics.app-ph↗

arXiv2022

Characterization of GaN-based HEMTs Down to 4.2 K for Cryogenic Applications

The cryogenic performance of GaN-based HEMTs (high-electron-mobility transistors) is systematically investigated by the direct current (DC) and low-frequency noise (LFN) characteristics within the temperature (T) range from 300 K to 4.2 K. The important electrical merits of the device, including drain saturation current (IDsat), on-resistance (RON), transductance, subthreshold swing (SS), gate leakage current, and Schottky barrier height, are comprehensively characterized and their temperature-dependent behavior was statistically analyzed. In addition, the LFN of the device shows an evident behavior of 1/f noise from 10 Hz to 10 kHz in the measured temperature range and can be significantly reduced at cryogenic temperature. These results are of great importance to motivate further studies into the GaN-based cryo-devices and systems.

physics.app-ph↗

arXiv2022

Design of Cryogenic Fully Differential Gain Boosting-OTA by the $g_{m}/I_{d}$ methodology used for a 14 bit Pipelined-SAR ADC

Quantum computing (QC) requires cryogenic electronic circuits as control and readout sub-systems of quantum chips to meet the qubit scale-up challenges.At this temperature,MOSFETs transistors exhibition many changes such as higher threshold voltage,higher mobility,and steeper substhreshold slope.We present a cryogenic fully differential gain boosting-OTA used for a 14 bit Pipelined-SAR ADC operating at 4.2K as the readout circuit for semiconductor-based quantum computing system.Using $g_{m}/I_{d}$ methodology to get pre-computed lookup tables based on the cryogenic 110nm BSIM4 model.The proposed OTA achieves very high unity-gain frequency@1.23GHz and open-loop low frequency gain@101dB.The total power consumption is 2.66mW at 4.2K,and a setting accuracy better than 0.01\% with $f_{-3dB}$ of 37MHz in a closed-loop application.

physics.app-ph↗

arXiv2021

Hot Carrier Degradation in MOSFETs at Cryogenic Temperatures Down to 4.2 K

Wide attention has been focused on cryogenic CMOS (Cryo-CMOS) operation because of its wide application and the improvement of CMOS performance. However, hot carrier degradation (HCD) becomes worsening at cryogenic temperature, which affects the reliability of Cryo-CMOS. Therefore, this article investigates HCD in 0.18 um bulk CMOS at cryogenic temperature down to 4.2 K. Particularly, the relationship between HCD and the current overshoot phenomenon and the influence of substrate bias on HCD are discussed. Besides, we predict the lifetime of the device at 77 K and 4.2 K. It is concluded that cryogenic NMOS cannot reach the ten years' commercial standard lifetime at standard drain voltage (VDD). And it is predicted that the reliability requirements can be reached when VDD<1.768V/1.734V at 77K/4.2K. Differently, the lifetime of PMOS is long enough even at low temperatures.

physics.app-ph↗

arXiv2021

Cryogenic Modeling of MOSFET Device Based on BSIM and EKV Models

Kink effect is a large obstacle for the cryogenic model of inversion-type bulk silicon MOSFET devices. This letter used two methods to correct the kink effect: the modified evolutionary strategy (MES) and dual-model modeling (BSIM3v3 and EKV2.6). Both methods are based on the principle of kink effect. The first method considers impact ionization and substrate current induced body effect (SCBE), and the other considers the change of the freeze-out substrate potential. By applying the above two methods, kink can be corrected to improve the agreement between simulation data and measurement data, and obtain more accurate model parameters. These two methods can be used in further work for cryogenic device modeling and circuit design.

physics.app-ph↗

arXiv2021

Characterization and Modeling of Native MOSFETs Down to 4.2 K

The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300K to 4.2K. The cryogenic Vth increases up to ~0.25V (W/L=10um/10um) and the improved subthreshold swing (SS)~14.30mV/dec@4.2K. The off-state current (Ioff) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different sub-bands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300K to 4.2K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.

physics.app-ph↗

arXiv2019

Characterization of 0.18μm CMOS Ring Oscillator at Liquid Helium Temperature

This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of CMOS at LHT are presented. The temperature-dependent device parameters are revised and the model then shows good agreement with the measurement results. The ring oscillator is then designed with energy efficiency optimization by application of forward body biasing (FBB). FBB is proposed to compensate for the threshold voltage (VTH) shift to preserve the benefits of the enhancement of the carrier mobility at 4.2K. The delay per stage (τp), the static current (ISTAT), the dynamic current (IDYN), the power dissipation (P) and the phase noise (L(foff)) are analyzed at both 298 K and 4.2 K, with and without FBB. The performance of the designed RO in terms of speed (τp=179ps), static current (23.55nA/stage), power dissipation (2.13μW) and phase noise (-177.57dBc/Hz@1MHz) can be achieved at 4.2K with the supply voltage (VDD) reduced to 0.9V.

physics.app-ph↗

arXiv2019

Cryogenic low power CMOS analog buffer at 4.2K

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/us and -93 V/us for 10 pF capacitive load. The static power of the circuit is only 79uW.

physics.app-ph↗

arXiv2019

Cryogenic Characerization and Modeling of Standard CMOS down to Liquid Helium Temperature for Quantum Computing

Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(Vth) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to 4.2K. A simple subcircuit was built to correct the kink effect. This work provides experimental evidence for implementation of cryogenic CMOS technology, a valid industrial tape-out process model, and romotes the application of integrated circuits in cryogenic environments, including quantum measurement and control systems for quantum chips at very low temperatures.

physics.app-ph↗

arXiv2018

Characterization and Modeling of 0.18μm CMOS Technology at sub-Kelvin Temperature

Previous cryogenic electronics studies are most above 4.2K. In this paper we present the cryogenic characterization of a 0.18μm standard bulk CMOS technology(1.8V and 5V) at sub-kelvin temperature around 270mK. PMOS and NMOS devices with different width to length ratios(W/L) are tested and characterized under various bias conditions at temperatures from 300K to 270mK. It is shown that the 0.18μm standard bulk CMOS technology is still working at sub-kelvin temperature. The kink effect and current overshoot phenomenon are observed at sub-kelvin temperature. Especially, current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of large and thin-oxide devices at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.

physics.app-ph↗

arXiv2018

MOSFET Characterization and Modeling at Cryogenic Temperatures

Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes. However, CMOS characteristics for various width/length (W/L) ratios and under different bias conditions still require further research. In addition, no previous works have produced an integrated modeling process for cryo-CMOS technology. In this paper, the results of characterization of Semiconductor Manufacturing International Corporation (SMIC) 0.18 μm CMOS technology at cryogenic temperatures (varying from 300 K to 4.2 K) are presented. Measurements of thin- and thick-oxide NMOS and PMOS devices with different W/L ratios are taken under four distinct bias conditions and at different temperatures. The temperature-dependent parameters are revised and an advanced CMOS model is proposed based on BSIM3v3 at the liquid nitrogen temperature (LNT). The proposed model ensures precision at the LNT and is valid for use in an industrial tape-out process. The proposed method presents a calibration approach for BSIM3v3 that is available at different temperature intervals.

physics.app-ph↗

arXiv2018

Engineering and Economic Analysis for Electric Vehicle Charging Infrastructure --- Placement, Pricing, and Market Design

This dissertation is to study the interplay between large-scale electric vehicle (EV) charging and the power system. We address three important issues pertaining to EV charging and integration into the power system: (1) charging station placement, (2) pricing policy and energy management strategy, and (3) electricity trading market and distribution network design to facilitate integrating EV and renewable energy source (RES) into the power system. For charging station placement problem, we propose a multi-stage consumer behavior based placement strategy with incremental EV penetration rates and model the EV charging industry as an oligopoly where the entire market is dominated by a few charging service providers (oligopolists). The optimal placement policy for each service provider is obtained by solving a Bayesian game. For pricing and energy management of EV charging stations, we provide guidelines for charging service providers to determine charging price and manage electricity reserve to balance the competing objectives of improving profitability, enhancing customer satisfaction, and reducing impact on the power system. Two algorithms --- stochastic dynamic programming (SDP) algorithm and greedy algorithm (benchmark algorithm) are applied to derive the pricing and electricity procurement strategy. We design a novel electricity trading market and distribution network, which supports seamless RES integration, grid to vehicle (G2V), vehicle to grid (V2G), vehicle to vehicle (V2V), and distributed generation (DG) and storage. We apply a sharing economy model to the electricity sector to stimulate different entities to exchange and monetize their underutilized electricity. A fitness-score (FS)-based supply-demand matching algorithm is developed by considering consumer surplus, electricity network congestion, and economic dispatch.

econ.EM↗

arXiv2018

Dynamic Pricing and Energy Management Strategy for EV Charging Stations under Uncertainties

This paper presents a dynamic pricing and energy management framework for electric vehicle (EV) charging service providers. To set the charging prices, the service providers faces three uncertainties: the volatility of wholesale electricity price, intermittent renewable energy generation, and spatial-temporal EV charging demand. The main objective of our work here is to help charging service providers to improve their total profits while enhancing customer satisfaction and maintaining power grid stability, taking into account those uncertainties. We employ a linear regression model to estimate the EV charging demand at each charging station, and introduce a quantitative measure for customer satisfaction. Both the greedy algorithm and the dynamic programming (DP) algorithm are employed to derive the optimal charging prices and determine how much electricity to be purchased from the wholesale market in each planning horizon. Simulation results show that DP algorithm achieves an increased profit (up to 9%) compared to the greedy algorithm (the benchmark algorithm) under certain scenarios. Additionally, we observe that the integration of a low-cost energy storage into the system can not only improve the profit, but also smooth out the charging price fluctuation, protecting the end customers from the volatile wholesale market.

eess.SP↗

arXiv2018

Multipath interference analysis of IR-UWB systems in indoor office LOS environment

Bit error rate (BER) performance of impulse radio Ultra-Wideband (UWB) systems in the presence of intrasymbol interference, inter-symbol interference, multiuser interference and addictive white Gaussian noise (AWGN) is presented in this paper. By analyzing the indoor office LOS channel model defined by IEEE 802.15.4a Task Group and deducing the variance for intra-symbol interference (IASI), inter-symbol interference (ISI) and multiuser interference (MUI), the system BER expression is obtained and verified by MATLAB simulations. Through comparing the simulation results with and without intra-symbol interference, the conclusion that intra-symbol interference cannot be neglected is drawn-moreover, such interference will significantly decrease performance of UWB based wireless sensor networks (WSN). Then, the BER performance of UWB systems in multiuser environment is also analyzed and analysis results show that multiuser interference will further worsen the transmission performance of UWB systems.

eess.SP↗