arXiv subjects

Diego R. Llanos

Publications and source records attributed to Diego R. Llanos.

5 recordsLinked to original sources

arXiv2026

Open Bitcoin Metrics: Verifiable Full-Node-Derived Bitcoin Time Series for Economic Research

Bitcoin research increasingly relies on on-chain indicators to study network activity, monetary issuance, transaction demand, miner incentives, coin-age behavior, and long-run monetary dynamics. However, many commonly used Bitcoin metrics are dispersed across commercial platforms, subject to heterogeneous definitions, or not fully reproducible from primary blockchain data. This manuscript introduces Open Bitcoin Metrics (OBM), a reproducible, full-node-derived dataset and reference guide for Bitcoin on-chain time series designed for economic and econometric research. The dataset provides documented daily series covering block production, block-space usage, transaction counts, supply, issuance, fees, miner revenue, mining difficulty, estimated hashrate, Bitcoin Days Destroyed, dormancy, liveliness, UTXO counts, spent output value, and related UTXO-age indicators. Metrics are reconstructed from a locally maintained Bitcoin Core full node, a persistent spent-output indexer, or deterministic transformations of previously generated OBM series. Each series is accompanied by open-source Python code, stable identifiers, explicit definitions, metadata, validation procedures, interpretive caveats, and comparisons with the closest publicly available metrics. The dataset is intended to support transparent empirical research, replication, teaching, and comparative analysis across monetary economics, financial economics, and blockchain studies.

cs.CE↗

arXiv2026

Instalación, configuración y utilización de un nodo Bitcoin en Linux

This paper documents the installation, configuration, and operation of a full Bitcoin node in a Linux environment, from manual compilation of the source code to complete synchronization with the network. The technical phases of the process are described, the main files generated by Bitcoin Core are analyzed, and the effects of the parameters txindex, prune, dbcache, maxmempool, and maxconnections are empirically studied. System resources during the block download (IBD) mechanism are also documented, and the operational importance of each resource is explained. This paper provides a solid foundation for future research proposals on Bitcoin node performance or for the development of blockchain data query tools.

cs.CR↗

arXiv2024

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL

As the interest in FPGA-based accelerators for HPC applications increases, new challenges also arise, especially concerning different programming and portability issues. This paper aims to provide a snapshot of the current state of the FPGA tooling and its problems. To do so, we evaluate the performance portability of two frameworks for developing FPGA solutions for HPC (SYCL and OpenCL) when using them to port a highly-parallel application to FPGAs, using both ND-range and single-task type of kernels. The developer's general recommendation when using FPGAs is to develop single-task kernels for them, as they are commonly regarded as more suited for such hardware. However, we discovered that, when using high-level approaches such as OpenCL and SYCL to program a highly-parallel application with no FPGA-tailored optimizations, ND-range kernels significantly outperform single-task codes. Specifically, while SYCL struggles to produce efficient FPGA implementations of applications described as single-task codes, its performance excels with ND-range kernels, a result that was unexpectedly favorable.

cs.DC↗

arXiv2024

Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools

As Field Programmable Gate Arrays (FPGAs) computing capabilities continue to grow, also does the interest on building scientific accelerators around them. Tools like Xilinx's High-Level Synthesis (HLS) help to bridge the gap between traditional high-level languages such as C and C++, and low-level hardware description languages such as VHDL and Verilog. In this report, we study the implementation of a fluid dynamics application, the Finite-Time Lyapunov Exponent (FTLE) calculation, on FPGA using HLS. We provide speed and resource-consumption results for 2- and 3-dimensional cases.

cs.AR↗

arXiv2023

Open SYCL on heterogeneous GPU systems: A case of study

Computational platforms for high-performance scientific applications are becoming more heterogenous, including hardware accelerators such as multiple GPUs. Applications in a wide variety of scientific fields require an efficient and careful management of the computational resources of this type of hardware to obtain the best possible performance. However, there are currently different GPU vendors, architectures and families that can be found in heterogeneous clusters or machines. Programming with the vendor provided languages or frameworks, and optimizing for specific devices, may become cumbersome and compromise portability to other systems. To overcome this problem, several proposals for high-level heterogeneous programming have appeared, trying to reduce the development effort and increase functional and performance portability, specifically when using GPU hardware accelerators. This paper evaluates the SYCL programming model, using the Open SYCL compiler, from two different perspectives: The performance it offers when dealing with single or multiple GPU devices from the same or different vendors, and the development effort required to implement the code. We use as case of study the Finite Time Lyapunov Exponent calculation over two real-world scenarios and compare the performance and the development effort of its Open SYCL-based version against the equivalent versions that use CUDA or HIP. Based on the experimental results, we observe that the use of SYCL does not lead to a remarkable overhead in terms of the GPU kernels execution time. In general terms, the Open SYCL development effort for the host code is lower than that observed with CUDA or HIP. Moreover, the SYCL version can take advantage of both CUDA and AMD GPU devices simultaneously much easier than directly using the vendor-specific programming solutions.

cs.DC↗