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Dmitri Mihhailov

Publications and source records attributed to Dmitri Mihhailov.

3 recordsLinked to original sources

Design and performance of the Fast Beam Condition Monitor for luminosity and background measurement at the CMS Experiment in LHC Run 3

The Fast Beam Condition Monitor (BCM1F) has been used at the CMS Experiment since the first LHC circulating beams in 2008. Originally meant as a beam-induced background monitor for fast beam losses detection, it showed a potential also for luminosity measurements in 2012 running, and has been used for luminosity measurements since the beginning of Run 2 data taking in 2015 as a part of the Beam Radiation, Instrumentation and Luminosity (BRIL) system. Over the years, the system has undergone various upgrades to the sensors, the front-end and back-end electronics, providing improvements in the precision of the measurements, that remain valid in the higher pileup conditions of LHC Run 3 (2022-2026). Based on the experience of all BCM1F Run 2 upgrades, the detector was completely rebuilt prior to LHC Run 3 using AC-coupled silicon-pad diodes and active cooling. This latest detector version exhibits excellent linearity with instantaneous luminosity and achieves nanosecond-level timing precision, enabling improved systematic corrections for luminosity and background measurements. This paper presents a detailed overview of the detector system for LHC Run 3, including the selection and qualification of sensors as well as a summary of the readout system. It also outlines the processing and calibration strategy for luminosity data, discussing operational hurdles and comparing BCM1F measurements to other CMS luminosity measurements to assess the system's performance as a luminometer. Lastly, the implications for the design of a future luminosity detector to be used in the envisioned HL-LHC upgrade are discussed.

physics.ins-det

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis

The planned high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will bring much higher data rates that are far above the capabilities of currently installed software-based data processing systems. Therefore, new methods must be used to facilitate on-the-fly extraction of scientifically significant information from the immense flow of data produced by LHC particle detectors. This paper focuses on implementation of a tau lepton triggering algorithm in FPGA. Due to the algorithm's complexity and strict technical requirements, its implementation in FPGA fabric becomes a particularly challenging task. The paper presents a study of algorithm development with the help of High-Level Synthesis (HLS) technique that can generate hardware description from C++ code. Various architectural solutions and optimizations that were tried out during the design architecture exploration process are also discussed in the paper.

cs.AR

HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study

With the current increase in the data produced by the Large Hadron Collider (LHC) at CERN, it becomes important to process this data in a corresponding manner. To begin with, to efficiently select events that contain relevant information from a massive flow of data. This is the task of the tau lepton decay triggering algorithm. The implementation is based on the High-Level Synthesis (HLS) approach that allows generating a hardware description of the design from the algorithm written in a high-level programming language like C++. HLS tools are intended to decrease the time and complexity of hardware design development, however, their capabilities are limited. The development of an efficient application requires substantial knowledge of the hardware design and HLS specifics. This paper presents the optimizations introduced to the algorithm that improved latency and area and more importantly solved the problems with the routing, making it possible to implement the algorithm on the FPGA fabric.

cs.AR