arXiv subjects

Dominique Drouin

Publications and source records attributed to Dominique Drouin.

At least 19 recordsLinked to original sources

arXiv2026

Functional Interface Blocks for Neuromorphic Hardware: A Junction-Centered Framework

Heterogeneous neuromorphic hardware integrates devices with dissimilar electrical characteristics and dynamics, making functional compatibility at their interconnections a primary design challenge. Direct coupling alone is insufficient to ensure correct operation, because the load-line conditions established at each junction determine the effective operating regime. Here, we propose a junction-centered interface framework in which inter-device connections are described through assigned drive/sense roles and organized into canonical functional interface blocks. As a concrete hardware realization, a second-generation current conveyor (CCII)-based implementation is then adopted as a composite realization of these interface primitives. The framework is validated experimentally in a Pavlovian-conditioning demonstrator combining a memristive synapse with a unijunction-transistor (UJT) post-neuron. By linking local junction conditions to reusable interface functions, the proposed methodology provides a systematic basis for the design and analysis of heterogeneous neuromorphic systems.

cs.ET↗

arXiv2026

Die to wafer direct bonding of (100) single-crystal diamond thin films for quantum optoelectronics

This work unlocks the manufacturing of nanophotonic quantum systems that exploit the unique material properties of single-crystal diamond (SCD). We achieve this by introducing a semiconductor-compatible process for the direct bonding of multiple high-quality, ultrathin diamond films onto a carrier wafer, enabling the subsequent parallel nanofabrication of optoelectronic integrated circuits. Central to this approach is a new diamond surface-preparation method that avoids boiling tri-acid mixtures while producing exceptionally clean 20 um thin single crystals. These platelets are bonded side-by-side to 100 mm silica wafers and exhibit a record shear strength of 45.1 MPa for (100)-oriented diamond, surpassing all previously reported bonding attempts. Evidence indicates that the bonding is dominated by van der Waals interactions, likely arising from mismatched protonation mechanisms between Si-OH and C-OH surface terminations, rather than from covalent-bond-driven mechanisms. Despite this non-molecular nature, the heterostructures remain stable through liquid immersions and standard nanofabrication steps. Because the method depends primarily on surface cleanliness and roughness rather than specific chemistries, it is broadly transferable across wafer materials. This capability to parallel-bond ultrathin SCD films onto large-area substrates provides a scalable route to high-performance platforms spanning nanophotonic quantum technologies, high-power electronics, MEMS, and biotechnology.

quant-ph↗

arXiv2025

Unsupervised local learning based on voltage-dependent synaptic plasticity for resistive and ferroelectric synapses

The deployment of AI on edge computing devices faces significant challenges related to energy consumption and functionality. These devices could greatly benefit from brain-inspired learning mechanisms, allowing for real-time adaptation while using low-power. In-memory computing with nanoscale resistive memories may play a crucial role in enabling the execution of AI workloads on these edge devices. In this study, we introduce voltage-dependent synaptic plasticity (VDSP) as an efficient approach for unsupervised and local learning in memristive synapses based on Hebbian principles. This method enables online learning without requiring complex pulse-shaping circuits typically necessary for spike-timing-dependent plasticity (STDP). We show how VDSP can be advantageously adapted to three types of memristive devices (TiO$_2$, HfO$_2$-based metal-oxide filamentary synapses, and HfZrO$_4$-based ferroelectric tunnel junctions (FTJ)) with disctinctive switching characteristics. System-level simulations of spiking neural networks incorporating these devices were conducted to validate unsupervised learning on MNIST-based pattern recognition tasks, achieving state-of-the-art performance. The results demonstrated over 83% accuracy across all devices using 200 neurons. Additionally, we assessed the impact of device variability, such as switching thresholds and ratios between high and low resistance state levels, and proposed mitigation strategies to enhance robustness.

cs.NE↗

arXiv2025

Rapid Autotuning of a SiGe Quantum Dot into the Single-Electron Regime with Machine Learning and RF-Reflectometry FPGA-Based Measurements

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the FPGA embedded in Keysight's Quantum Engineering Toolkit (QET), the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

cond-mat.mes-hall↗

arXiv2025

Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction

This paper presents a novel approach utilizing a scalable neural decoder application-specific integrated circuit (ASIC) based on metal oxide memristors in a 180nm CMOS technology. The ASIC architecture employs in-memory computing with memristor crossbars for efficient vector-matrix multiplications (VMM). The ASIC decoder architecture includes an input layer implemented with a VMM and an analog sigmoid activation function, a recurrent layer with analog memory, and an output layer with a VMM and a threshold activation function. Cryogenic characterization of the ASIC is conducted, demonstrating its performance at both room temperature and cryogenic temperatures down to 1.2K. Results indicate stable activation function shapes and pulse responses at cryogenic temperatures. Moreover, power consumption measurements reveal consistent behavior at room and cryogenic temperatures. Overall, this study lays the foundation for developing efficient and scalable neural decoders for quantum error correction in cryogenic environments.

quant-ph↗

arXiv2024

Experimental online quantum dots charge autotuning using neural networks

Spin-based semiconductor qubits hold promise for scalable quantum computing, yet they require reliable autonomous calibration procedures. This study presents an experimental demonstration of online single-dot charge autotuning using a convolutional neural network integrated into a closed-loop calibration system. The autotuning algorithm explores the gates' voltage space to localize charge transition lines, thereby isolating the one-electron regime without human intervention. This exploration leverages the model's uncertainty estimation to find the appropriate gate configuration with minimal measurements while reducing the risk of failures. In 20 experimental runs, our method achieved a success rate of 95% in locating the target electron regime, highlighting the robustness of this approach against noise and distribution shifts from the offline training set. Each tuning run lasted an average of 2 hours and 9 minutes, primarily due to the limited speed of the current measurement. This work validates the feasibility of machine learning-driven real-time charge autotuning for quantum dot devices, advancing the development toward the control of large qubit arrays.

cond-mat.mes-hall↗

arXiv2024

Versatile CMOS Analog LIF Neuron for Memristor-Integrated Neuromorphic Circuits

Heterogeneous systems with analog CMOS circuits integrated with nanoscale memristive devices enable efficient deployment of neural networks on neuromorphic hardware. CMOS Neuron with low footprint can emulate slow temporal dynamics by operating with extremely low current levels. Nevertheless, the current read from the memristive synapses can be higher by several orders of magnitude, and performing impedance matching between neurons and synapses is mandatory. In this paper, we implement an analog leaky integrate and fire (LIF) neuron with a voltage regulator and current attenuator for interfacing CMOS neurons with memristive synapses. In addition, the neuron design proposes a dual leakage that could enable the implementation of local learning rules such as voltage-dependent synaptic plasticity. We also propose a connection scheme to implement adaptive LIF neurons based on two-neuron interaction. The proposed circuits can be used to interface with a variety of synaptic devices and process signals of diverse temporal dynamics.

cs.ET↗

arXiv2024

Robust quantum dots charge autotuning using neural network uncertainty

This study presents a machine-learning-based procedure to automate the charge tuning of semiconductor spin qubits with minimal human intervention, addressing one of the significant challenges in scaling up quantum dot technologies. This method exploits artificial neural networks to identify noisy transition lines in stability diagrams, guiding a robust exploration strategy leveraging neural networks' uncertainty estimations. Tested across three distinct offline experimental datasets representing different single quantum dot technologies, the approach achieves over 99% tuning success rate in optimal cases, where more than 10% of the success is directly attributable to uncertainty exploitation. The challenging constraints of small training sets containing high diagram-to-diagram variability allowed us to evaluate the capabilities and limits of the proposed procedure.

quant-ph↗

arXiv2024

Towards scalable cryogenic quantum dot biasing using memristor-based DC sources

Cryogenic memristor-based DC sources offer a promising avenue for in situ biasing of quantum dot arrays. In this study, we present experimental results and discuss the scaling potential for such DC sources. We first demonstrate the operation of a commercial discrete operational amplifier down to 1.2K which is used on the DC source prototype. Then, the tunability of the memristor-based DC source is validated by performing several 250mV-DC sweeps with a resolution of 10mV at room temperature and at 1.2K. Additionally, the DC source prototype exhibits a limited output drift of $\approx1\mathrm{\mu Vs^{-1}}$ at 1.2K. This showcases the potential of memristor-based DC sources for quantum dot biasing. Limitations in power consumption and voltage resolution using discrete components highlight the need for a fully integrated and scalable complementary metal-oxide-semiconductor-based (CMOS-based) approach. To address this, we propose to monolithically co-integrate emerging non-volatile memories (eNVMs) and 65nm CMOS circuitry. Simulations reveal a reduction in power consumption, down to $\mathrm{10\mu W}$ per DC source and in footprint. This allows for the integration of up to one million eNVM-based DC sources at the 4.2K stage of a dilution fridge, paving the way for near term large-scale quantum computing applications.

cs.ET↗

arXiv2023

Analog programming of CMOS-compatible Al$_2$O$_3$/TiO$_\textrm{2-x}$ memristor at 4.2 K after metal-insulator transition suppression by cryogenic reforming

The exploration of memristors' behavior at cryogenic temperatures has become crucial due to the growing interest in quantum computing and cryogenic electronics. In this context, our study focuses on the characterization at cryogenic temperatures (4.2 K) of TiO$_\textrm{2-x}$-based memristors fabricated with a CMOS-compatible etch-back process. We demonstrate a so-called cryogenic reforming (CR) technique performed at 4.2 K to overcome the well-known metal-insulator transition (MIT) which limits the analog behavior of memristors at low temperatures. This cryogenic reforming process was found to be reproducible and led to a durable suppression of the MIT. This process allowed to reduce by approximately 20% the voltages required to perform DC resistive switching at 4.2 K. Additionally, conduction mechanism studies of memristors before and after cryogenic reforming from 4.2 K to 300 K revealed different behaviors above 100 K, indicating a potential change in the conductive filament stoichiometry. The reformed devices exhibit a conductance level that is 50 times higher than ambient-formed memristor, and the conduction drop between 300 K and 4.2 K is 100 times smaller, indicating the effectiveness of the reforming process. More importantly, CR enables analog programming at 4.2 K with typical read voltages. Suppressing the MIT improved the analog switching dynamics of the memristor leading to approximately 250% larger on/off ratios during long-term depression (LTD)/long-term potentiation (LTP) resistance tuning. This enhancement opens up the possibility of using TiO$_{\textrm{2-x}}$-based memristors to be used as synapses in neuromorphic computing at cryogenic temperatures.

physics.app-ph↗

arXiv2023

A Cryogenic Memristive Neural Decoder for Fault-tolerant Quantum Error Correction

Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Its ability to adapt to hardware noise and long-term drifts make neural decoders a promising candidate for inclusion in a fault-tolerant quantum architecture. However, given their limited scalability, it is prudent that small-scale (local) neural decoders are treated as first stages of multi-stage decoding schemes for fault-tolerant quantum computers with millions of qubits. In this case, minimizing the decoding time to match the stabilization measurements frequency and a tight co-integration with the QPUs is highly desired. Cryogenic realizations of neural decoders can not only improve the performance of higher stage decoders, but they can minimize communication delays, and alleviate wiring bottlenecks. In this work, we design and analyze a neural decoder based on an in-memory computation (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the neural decoder and perform analog matrix-vector multiplications. In simulations supported by experimental measurements, we investigate the impact of TiOx-based memristive devices' non-idealities on decoding fidelity. We develop hardware-aware re-training methods to mitigate the fidelity loss, restoring the ideal decoder's pseudo-threshold for the distance-3 surface code. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated fault-tolerant QEC.

quant-ph↗

arXiv2023

Hardware-aware Training Techniques for Improving Robustness of Ex-Situ Neural Network Transfer onto Passive TiO2 ReRAM Crossbars

Passive resistive random access memory (ReRAM) crossbar arrays, a promising emerging technology used for analog matrix-vector multiplications, are far superior to their active (1T1R) counterparts in terms of the integration density. However, current transfers of neural network weights into the conductance state of the memory devices in the crossbar architecture are accompanied by significant losses in precision due to hardware variabilities such as sneak path currents, biasing scheme effects and conductance tuning imprecision. In this work, training approaches that adapt techniques such as dropout, the reparametrization trick and regularization to TiO2 crossbar variabilities are proposed in order to generate models that are better adapted to their hardware transfers. The viability of this approach is demonstrated by comparing the outputs and precision of the proposed hardware-aware network with those of a regular fully connected network over a few thousand weight transfers using the half moons dataset in a simulation based on experimental data. For the neural network trained using the proposed hardware-aware method, 79.5% of the test set's data points can be classified with an accuracy of 95% or higher, while only 18.5% of the test set's data points can be classified with this accuracy by the regularly trained neural network.

cs.AR↗

arXiv2023

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses

In this work we report a study and a co-design methodology of an analog SNN crossbar output circuit designed in a 28nm FD-SOI technology node that comprises a tunable current attenuator and a leak-integrate and fire neurons that would enable the integration of emerging non-volatile memories (eNVMs) for synaptic arrays based on various technologies including phase change (PCRAM), oxide-based (OxRAM), spin transfer and spin orbit torque magnetic memories (STT, SOT-MRAM). Circuit SPICE simulation results and eNVM experimental data are used to showcase and estimate the neurons fan-in for each type of eNVM considering the technology constraints and design trade-offs that set its limits such as membrane capacitance and supply voltage, etc.

eess.SY↗

arXiv2022

Voltage-Dependent Synaptic Plasticity (VDSP): Unsupervised probabilistic Hebbian plasticity rule based on neurons membrane potential

This study proposes voltage-dependent-synaptic plasticity (VDSP), a novel brain-inspired unsupervised local learning rule for the online implementation of Hebb's plasticity mechanism on neuromorphic hardware. The proposed VDSP learning rule updates the synaptic conductance on the spike of the postsynaptic neuron only, which reduces by a factor of two the number of updates with respect to standard spike-timing-dependent plasticity (STDP). This update is dependent on the membrane potential of the presynaptic neuron, which is readily available as part of neuron implementation and hence does not require additional memory for storage. Moreover, the update is also regularized on synaptic weight and prevents explosion or vanishing of weights on repeated stimulation. Rigorous mathematical analysis is performed to draw an equivalence between VDSP and STDP. To validate the system-level performance of VDSP, we train a single-layer spiking neural network (SNN) for the recognition of handwritten digits. We report 85.01 $ \pm $ 0.76% (Mean $ \pm $ S.D.) accuracy for a network of 100 output neurons on the MNIST dataset. The performance improves when scaling the network size (89.93 $ \pm $ 0.41% for 400 output neurons, 90.56 $ \pm $ 0.27 for 500 neurons), which validates the applicability of the proposed learning rule for spatial pattern recognition tasks. Future work will consider more complicated tasks. Interestingly, the learning rule better adapts than STDP to the frequency of input signal and does not require hand-tuning of hyperparameters

cs.NE↗

arXiv2022

Memristor-based cryogenic programmable DC sources for scalable in-situ quantum-dot control

Current quantum systems based on spin qubits are controlled by classical electronics located outside the cryostat at room temperature. This approach creates a major wiring bottleneck, which is one of the main roadblocks toward truly scalable quantum computers. Thus, we propose a scalable memristor-based programmable DC source that could be used to perform biasing of quantum dots inside of the cryostat (i.e. in-situ). This novel cryogenic approach would enable to control the applied voltage on the electrostatic gates by programming the resistance of the memristors, thus storing in the latter the appropriate conditions to form the quantum dots. In this study, we first demonstrate multilevel resistance programming of a TiO2-based memristors at 4.2 K, an essential feature to achieve voltage tunability of the memristor-based DC source. We then report hardwarebased simulations of the electrical performance of the proposed DC source. A cryogenic TiO2-based memristor model fitted on our experimental data at 4.2 K was used to show a 1 V voltage range and 100 uV in-situ memristor-based DC source. Finally, we simulate the biasing of double quantum dots enabling sub-2 minutes in-situ charge stability diagrams. This demonstration is a first step towards more advanced cryogenic applications for resistive memories such as cryogenic control electronics for quantum computers.

cs.AR↗

arXiv2021

Fully CMOS-compatible passive TiO2-based memristor crossbars for in-memory computing

Brain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current computing paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due to their ability to natively perform in-memory computing and fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need to be compatible with fabrication processes and materials of industrial CMOS technologies. Herein, we report a complete CMOS-compatible fabrication process of TiO2-based passive memristor crossbars with 700 nm wide electrodes. We show successful bottom electrode fabrication by a damascene process, resulting in an optimised topography and a surface roughness as low as 1.1 nm. DC sweeps and voltage pulse programming yield statistical results related to synaptic-like multilevel switching. Both cycle-to-cycle and device-to-device variability are investigated. Analogue programming of the conductance using sequences of 200 ns voltage pulses suggest that the fabricated memories have a multilevel capacity of at least 3 bits due to the cycle-to-cycle reproducibility.

cs.ET↗

arXiv2021

Miniaturizing neural networks for charge state autotuning in quantum dots

A key challenge in scaling quantum computers is the calibration and control of multiple qubits. In solid-state quantum dots, the gate voltages required to stabilize quantized charges are unique for each individual qubit, resulting in a high-dimensional control parameter space that must be tuned automatically. Machine learning techniques are capable of processing high-dimensional data - provided that an appropriate training set is available - and have been successfully used for autotuning in the past. In this paper, we develop extremely small feed-forward neural networks that can be used to detect charge-state transitions in quantum dot stability diagrams. We demonstrate that these neural networks can be trained on synthetic data produced by computer simulations, and robustly transferred to the task of tuning an experimental device into a desired charge state. The neural networks required for this task are sufficiently small as to enable an implementation in existing memristor crossbar arrays in the near future. This opens up the possibility of miniaturizing powerful control elements on low-power hardware, a significant step towards on-chip autotuning in future quantum dot computers.

cond-mat.mes-hall↗

arXiv2021

Signals to Spikes for Neuromorphic Regulated Reservoir Computing and EMG Hand Gesture Recognition

Surface electromyogram (sEMG) signals result from muscle movement and hence they are an ideal candidate for benchmarking event-driven sensing and computing. We propose a simple yet novel approach for optimizing the spike encoding algorithm's hyper-parameters inspired by the readout layer concept in reservoir computing. Using a simple machine learning algorithm after spike encoding, we report performance higher than the state-of-the-art spiking neural networks on two open-source datasets for hand gesture recognition. The spike encoded data is processed through a spiking reservoir with a biologically inspired topology and neuron model. When trained with the unsupervised activity regulation CRITICAL algorithm to operate at the edge of chaos, the reservoir yields better performance than state-of-the-art convolutional neural networks. The reservoir performance with regulated activity was found to be 89.72% for the Roshambo EMG dataset and 70.6% for the EMG subset of sensor fusion dataset. Therefore, the biologically-inspired computing paradigm, which is known for being power efficient, also proves to have a great potential when compared with conventional AI algorithms.

eess.SP↗