arXiv subjects

Dominique Drouin

Publications and source records attributed to Dominique Drouin.

27 records · Page 2Linked to original sources

arXiv2021

Oxygen vacancy engineering of TaOx-based resistive memories by Zr doping for improved variability and synaptic behavior

Resistive switching devices are promising emerging non-volatile memories. However, one of the biggest challenges for resistive switching (RS) memory applications is the device-to-device (D2D) variability which is related to the intrinsic stochastic formation and configuration of oxygen vacancy (VO) conductive filaments. In order to reduce D2D variability, the control of oxygen vacancy formation and configuration is paramount. We report in this study Zr doping of TaOx-based RS devices prepared by pulsed laser deposition (PLD) as an efficient mean to reduce VO formation energy and increase conductive filament (CF) confinement, thus reducing D2D variability. Such findings were supported by X-ray photoelectron spectroscopy (XPS), spectroscopic ellipsometry (SE) and electronic transport analysis. Zr doped films presented increased VO concentration, and more localized VO thanks to the interaction with Zr. According to DC and pulse mode electrical characterization, D2D variability was decreased by a factor of 7, resistance window was doubled and a more gradual and monotonic long-term potentiation/depression (LTP/LTD) in pulse switching was achieved in forming-free Zr:TaOx devices thus displaying promising performance for artificial synapse applications.

physics.app-ph↗

arXiv2021

Dynamic formation of spherical voids crossing linear defects

A predictive model for the evolution of porous Ge layer upon thermal treatment is reported. We represent an idealized etched dislocation core as an axially symmetric elongated hole and computed its dynamics during annealing. Numerical simulations of the shape change of a completely spherical void via surface diffusion have been performed. Simulations and experiments show individual large spherical voids, aligned along the dislocation core. The creation of voids could facilitate interactions between dislocations, enabling the dislocation network to change its connectivity in a way that facilitates the subsequent annihilation of dislocation segments. This confirms that thermally activated processes such as state diffusion of porous materials provide mechanisms whereby the defects are removed or arranged in configurations of lower energy. This model is intended to be indicative, and more detailed experimental characterization of process parameters such as annealing temperature and time, and could estimate the annealing time for given temperatures, or vice versa, with the right parameters.

cond-mat.mtrl-sci↗

arXiv2020

AIDX: Adaptive Inference Scheme to Mitigate State-Drift in Memristive VMM Accelerators

An adaptive inference method for crossbar (AIDX) is presented based on an optimization scheme for adjusting the duration and amplitude of input voltage pulses. AIDX minimizes the long-term effects of memristance drift on artificial neural network accuracy. The sub-threshold behavior of memristor has been modeled and verified by comparing with fabricated device data. The proposed method has been evaluated by testing on different network structures and applications, e.g., image reconstruction and classification tasks. The results showed an average of 60% improvement in convolutional neural network (CNN) performance on CIFAR10 dataset after 10000 inference operations as well as 78.6% error reduction in image reconstruction.

cs.ET↗

arXiv2020

Conductive filament evolution dynamics revealed by cryogenic (1.5 K) multilevel switching of CMOS-compatible Al2O3/TiO2 resistive memories

This study demonstrates multilevel switching at 1.5 K of Al2O3/TiO2-x resistive memory devices fabricated with CMOS-compatible processes and materials. The I-V characteristics exhibit a negative differential resistance (NDR) effect due to a Joule-heating-induced metal-insulator transition of the Ti4O7 conductive filament. Carrier transport analysis of all multilevel switching I-V curves show that while the insulating regime follows the space charge limited current (SCLC) model for all resistance states, the conduction in the metallic regime is dominated by SCLC and trap-assisted tunneling (TAT) for low- and high-resistance states respectively. A non-monotonic conductance evolution is observed in the insulating regime, as opposed to the continuous and gradual conductance increase and decrease obtained in the metallic regime during the multilevel SET and RESET operations. Cryogenic transport analysis coupled to an analytical model accounting for the metal-insulator-transition-induced NDR effects and the resistance states of the device provide new insights on the conductive filament evolution dynamics and resistive switching mechanisms. Our findings suggest that the non-monotonic conductance evolution in the insulating regime is due to the combined effects of longitudinal and radial variations of the Ti4O7 conductive filament during the switching. This behavior results from the interplay between temperature- and field-dependent geometrical and physical characteristics of the filament.

physics.app-ph↗

arXiv2019

Observation of Highly Nonlinear Resistive Switching of Al2O3/TiO2-x Memristors at Cryogenic Temperature (1.5 K)

In this work, we investigate the behavior of Al2O3/TiO2-x cross-point memristors in cryogenic environment. We report successful resistive switching of memristor devices from 300 K down to 1.5 K. The I-V curves exhibit negative differential resistance effects between 130 and 1.5 K, attributed to a metal-insulator transition (MIT) of the Ti4O7 conductive filament. The resulting highly nonlinear behavior is associated to a maximum ION/IOFF ratio of 84 at 1.5 K, paving the way to selector-free cryogenic passive crossbars. Finally, temperature-dependant thermal activation energies related to the conductance at low bias (20 mV) are extracted for memristors in low resistance state, suggesting hopping-type conduction mechanisms.

physics.app-ph↗

arXiv2019

FPGA-based Multi-Chip Module for High-Performance Computing

Current integration, architectural design and manufacturing technologies are not suited for the computing density and power efficiency requested by Exascale computing. New approaches in hardware architecture are thus needed to overcome the technological barriers preventing the transition to the Exascale era. In that scope, we report successful fabrication of first ExaNoDe's MCM prototypes dedicated to Exascale computing applications. Each MCM was composed of 2 Xilinx Zynq Ultrascale+ MPSoC, assembled on advanced 68.5 mm x 55 mm laminate substrates specifically designed and fabricated for the project. Acoustic microscopy, x-ray, cross-section and Thermo-Moire investigations revealed no voids, shorts, delamination, cracks or warpage issues. Two MCMs were mounted on a daughter board by FORTH for testing purposes. The DDR memories on the 4 SODIMMs of the daughter board were successfully tested by running extensive Xilinx memory tests with clock frequencies of 1866 MHz and 2133 MHz. All 4 FPGAs were programmed with the Xilinx integrated bit error ratio test (IBERT) tailored for this board for links testing. All intra-board high-speed links between all FPGAs were stable at 10 Gbps, even under the more demanding 31-bit PRBS (Pseudorandom Binary Sequence) tests.

cs.AR↗

arXiv2018

Low cost Ge/Si virtual substrate through dislocation trapping by nanovoids

A low-cost method to reduce the threading disloca-tions density (TDD) in relaxed germanium (Ge) epilayers grown on silicon (Si) substrates is presented. Ge/Si sub-strate was treated with post epitaxial process to create a region with a high density of nanovoids in Ge layer which act as a barrier for threading dislocations propagation .

cond-mat.mtrl-sci↗

arXiv2014

A Silicon Nanocrystal Tunnel Field Effect Transistor

In this work, we demonstrate a silicon nanocrystal Field Effect Transistor (ncFET). Its operation is similar to that of a Tunnelling Field Effect Transistor (TFET) with two barriers in series. The tunnelling barriers are fabricated in very thin silicon dioxyde and the channel in intrinsic polycrystalline silicon. The absence of doping eliminates the problem of achieving sharp doping profiles at the junctions, which has proven a challenge for large-scale integration and in principle allows scaling down the atomic level. The demonstrated ncFET features a 10$^4$ on/off current ratio at room temperature, a low 30 pA/$μ$m leakage current at a 0.5 V bias, an on-state current on a par with typical all-Si TFETs and bipolar operation with high symmetry. Quantum dot transport spectroscopy is used to assess the band structure and energy levels of the silicon island.

cond-mat.mes-hall↗

arXiv2013

Inductively Coupled Plasma etching of amorphous silicon nanostructures over nanotopography using C4F8/SF6 chemistry

Inductively Coupled Plasma (ICP) etching of amorphous silicon (a-Si) nanostructures using a continuous C4F8/SF6 plasma over nanotopography in silicon dioxide (SiO2) is investigated. The coil power of the ICP system is used to tune the a-Si etch rate from 20 to 125 nm/min. The etch rates of a-Si, SiO2 and electroresist are measured depending on the SF6 ratio, platen power and chamber pressure and used to optimize the a-Si:SiO2 etch selectivity. The results on nanostructures show that the presence of an insulating etch-stop layer affects the passivation ratio required to achieve vertical sidewalls. A low pressure is also necessary in order to etch the silicon nanostructure embedded into the oxide nanotrenches to form a highly conformable a-Si nanowire. We argue that both of these behaviors could be explained by surface charging effects. Finally, etching of 20 nm a-Si nanowires that cross 15 nm trenches in oxide with vertical sidewalls and a 4.3:1 a-Si:SiO2 etch selectivity is demonstrated. This etching process can be used in applications where nanotopography is present such as single electron transistors or multigate transistors.

physics.plasm-ph↗