arXiv subjects

Eduard Alarcón

Publications and source records attributed to Eduard Alarcón.

At least 19 recordsLinked to original sources

arXiv2026

Quantum Circuit Pruning: From NISQ Architectures to Fault-Tolerant Operations

We present a routing-aware pruning strategy for quantum circuits that selectively removes parametric two-qubit gates whose computational contribution is outweighed by the fidelity cost of their execution, and assess it across both Noisy Intermediate-Scale Quantum (NISQ) and fault-tolerant quantum computing (FTQC) architectures. Each two-qubit gate of a circuit is evaluated by comparing an architecture-independent lower bound on the fidelity cost of omitting the gate against a hardware-specific model for the routing execution cost in each setting. We additionally provide an analytical characterization of the pruning boundary as a function of rotation angle, qubit distance, and hardware noise. Simulations on benchmark circuits demonstrate gate count reductions of up to 48.6% and fidelity improvements of up to 47.7% in the NISQ regime, while a feasibility analysis on FT hardware indicates that pruning is expected to remain relevant across a range of code distances and physical error rates. These results establish routing-aware pruning as a practical and unified compilation strategy across the quantum computing stack.

quant-ph↗

arXiv2026

Transversal Gates and Magic State Distillation in an Optimally Synthesized Spin-Qubit Shuttling Bus

Fault-tolerant quantum computing requires not only reliable logical qubit storage, but also the ability to perform high-fidelity logical operations between error-corrected qubits at scale. While much of the existing literature focuses on optimizing syndrome extraction for a single logical qubit, the co-design of physical architectures that support both robust error correction and efficient logical computation remains an open challenge. In this work, we propose a multi-qubit spin-qubit shuttling bus architecture that addresses both requirements simultaneously. The architecture optimizes the physical qubit layout for syndrome extraction and supports transversal two-qubit logical gates between an arbitrary number of logical qubits, achieving all-to-all logical connectivity through coherent spin shuttling. We further propose an ancilla-sharing scheme that encodes multiple logical qubits within a single logical element, compressing the physical footprint of the processor and improving long-range gate fidelity. Extending the architecture from a one-dimensional bus to a two-dimensional grid of shuttling tracks reduces the inter-qubit distance, yielding consistent improvements in logical error. Finally, we apply the Quantum Reverse Mapping methodology at the logical level to optimize the layout of a \textit{15-to-1} magic state distillation circuit, demonstrating how the transversal capabilities of the proposed architecture can be leveraged for universal fault-tolerant computation. Taken together, these results establish a principled co-design framework that bridges the physical, error-correction, and logical computation layers of the quantum stack, and demonstrate that spin-qubit shuttling architectures are a viable and flexible substrate for scalable fault-tolerant quantum computation.

quant-ph↗

arXiv2026

Energy efficiency of quantum computers

How much energy does a quantum computer consume? Are they more efficient than their classical counterparts? In this work, we make a step towards answering these questions. We define the energy efficiency of a quantum computer as the ratio of the number of algorithms it can perform during a given time over the energy consumed by the hardware during this time. We analyze the most representative physical platforms currently envisioned to be used as building blocks of quantum computers: superconducting qubits, silicon spin qubits, trapped ions, neutral atoms and photonic qubits. Including insights from experts in all these technologies and taking into account algorithm compilation constraints, we discuss the advantages and inconveniences of each platform from an energy standpoint. Beyond providing concrete values of the energy consumption of current quantum computers, we lay the foundation of a framework to benchmark the energy efficiency of any future quantum computing architecture.

quant-ph↗

arXiv2026

Channel-Aware Behavioral Power Modeling of CMOS OOK Transceivers for Wireless Network-on-Chip Systems

Wireless Network-on-Chip (WNoC) systems enable low-latency communication in many-core platforms through short-range wireless links. However, the power consumption of integrated transceivers (TRXs), dominated by that of the RF front-end circuitry, remains a major challenge. Moreover, the optimal operating frequency is still unclear, as bandwidth, energy efficiency, and technology maturity must be balanced. This work presents a channel-aware behavioral modeling framework to estimate power consumption and identify energy-efficient operating points in non-coherent On-Off Keying (OOK) TRXs over a wide frequency range. The approach leverages survey data from CMOS implementations to derive frequency-dependent power models for key TRX sub-blocks, including the power amplifier (PA), oscillator, mixer, low noise amplifier (LNA), and envelope detector (ED). By incorporating the frequency-dependent channel loss into the TRX power budget, the model captures system-level power trade-offs across operating regimes. The analysis reveals a frequency-dependent shift in power dominance between the transmitter and receiver: oscillator- and ED-dominated regimes at lower frequencies transition to PA- and LNA-dominated behavior at higher frequencies. Furthermore, the energy-per-bit landscape exhibits sweet spots and a model-based global minimum, indicating that optimal operation cannot be achieved by optimizing transmitter or receiver independently. Overall, the proposed framework enables rapid and physically grounded exploration of power scaling with frequency and channel conditions, providing practical guidelines for energy-efficient design of high-frequency wireless links for WNoC systems and beyond.

eess.SP↗

arXiv2026

Towards Emotion Recognition with 3D Pointclouds Obtained from Facial Expression Images

Facial Emotion Recognition is a critical research area within Affective Computing due to its wide-ranging applications in Human Computer Interaction, mental health assessment and fatigue monitoring. Current FER methods predominantly rely on Deep Learning techniques trained on 2D image data, which pose significant privacy concerns and are unsuitable for continuous, real-time monitoring. As an alternative, we propose High-Frequency Wireless Sensing (HFWS) as an enabler of continuous, privacy-aware FER, through the generation of detailed 3D facial pointclouds via on-person sensors embedded in wearables. We present arguments supporting the privacy advantages of HFWS over traditional 2D imaging, particularly under increasingly stringent data protection regulations. A major barrier to adopting HFWS for FER is the scarcity of labeled 3D FER datasets. Towards addressing this issue, we introduce a FLAME-based method to generate 3D facial pointclouds from existing public 2D datasets. Using this approach, we create AffectNet3D, a 3D version of the AffectNet database. To evaluate the quality and usability of the generated data, we design a pointcloud refinement pipeline focused on isolating the facial region, and train the popular PointNet++ model on the refined pointclouds. Fine-tuning the model on a small subset of the unseen 3D FER dataset BU-3DFE yields a classification accuracy exceeding 70%, comparable to oracle-level performance. To further investigate the potential of HFWS-based FER for continuous monitoring, we simulate wearable sensing conditions by masking portions of the generated pointclouds. Experimental results show that models trained on AffectNet3D and fine-tuned with just 25% of BU-3DFE outperform those trained solely on BU-3DFE. These findings highlight the viability of our pipeline and support the feasibility of continuous, privacy-aware FER via wearable HFWS systems.

cs.CV↗

arXiv2026

Synthesizing an Optimal Spin Qubit Shuttling Bus Architecture for the Surface Code

As quantum computers scale toward millions of physical qubits, it becomes essential to robustly encode individual logical qubits to ensure fault tolerance under realistic noise. A high-quality foundational encoding allows future compilation techniques and heuristics to build on optimal or near-optimal layouts, improving scalability and error resilience. In this work, we synthesize a one-dimensional shuttling bus architecture for the rotated surface code, leveraging coherent spin-qubit shuttling, following a novel methodology we name Quantum Reverse Mapping. We formulate a mixed-integer optimization model that yields optimal solutions with relatively low execution time for small code distances, and propose a scalable heuristic that matches optimal results while maintaining linear computational complexity. We evaluate the synthesized architecture using architectural metrics, such as shuttling distance and cycle time, and full quantum simulations under realistic noise models, showing that the proposed design can sustain logical error rates as low as $2\times 10^{-10}$ per round at code distance 21, showcasing its feasibility for scalable quantum error correction in spin-based quantum processors.

quant-ph↗

arXiv2026

Towards Scalable Multi-Chip Wireless Networks with Near-Field Time Reversal

The concept of Wireless Network-on-Chip (WNoC) has emerged as a potential solution to address the escalating communication demands of modern computing systems due to its low-latency, versatility, and reconfigurability. However, for WNoC to fulfill its potential, it is essential to establish multiple high-speed wireless links across chips. Unfortunately, the compact and enclosed nature of computing packages introduces significant challenges in the form of Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), which not only hinder the deployment of multiple spatial channels, but also severely restrict the symbol rate of each individual channel. In this paper, we posit that Time Reversal (TR) could be effective in addressing both impairments in this static scenario, thanks to its spatiotemporal focusing capabilities even in the near-field. Through comprehensive full-wave simulations and bit error rate analysis in multiple chip layouts with multiple frequency bands, we provide evidence that TR can increase the symbol rate by an order of magnitude, enabling the deployment of multiple concurrent links and achieving aggregate speeds exceeding 100 Gb/s. Finally, we evaluate the impact of reducing the sampling rate of the TR filter on the achievable speeds, paving the way to practical TR-based wireless communications at the chip scale.

cs.ET↗

arXiv2026

Quantum Circuit Pruning: Improving Fidelity via Compilation-Aware Circuit Approximation

This work presents a routing-aware pruning strategy for quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) devices. We propose a method to remove parametric controlled rotations whose small rotation angles do not justify the routing overhead required for their implementation. By selectively pruning such gates, the method mitigates fidelity loss arising from additional SWAP operations introduced during compilation. Our approach evaluates whether executing a gate leads to greater fidelity loss than omitting it. Simulations on benchmark circuits with realistic noise models show that the method reduces two-qubit gate counts (up to 48.6%) while improving final state fidelity (up to 47.7%), especially for larger circuits where routing costs dominate.

quant-ph↗

arXiv2025

Characterizing Scaling Trends of Post-Compilation Circuit Resources for NISQ-era QML Models

This work investigates the scaling characteristics of post-compilation circuit resources for Quantum Machine Learning (QML) models on connectivity-constrained NISQ processors. We analyze Quantum Kernel Methods and Quantum Neural Networks across processor topologies (linear, ring, grid, star), focusing on SWAP overhead, circuit depth, and two-qubit gate count. Our findings reveal that entangling strategy significantly impacts resource scaling, with circular and shifted circular alternating strategies showing steepest scaling. Ring topology demonstrates slowest resource scaling for most QML models, while Tree Tensor Networks lose their logarithmic depth advantage after compilation. Through fidelity analysis under realistic noise models, we establish quantitative relationships between hardware improvements and maximum reliable qubit counts, providing crucial insights for hardware-aware QML model design across the full-stack architecture.

quant-ph↗

arXiv2025

Quantum Computing for Large-scale Network Optimization: Opportunities and Challenges

The complexity of large-scale 6G-and-beyond networks demands innovative approaches for multi-objective optimization over vast search spaces, a task often intractable. Quantum computing (QC) emerges as a promising technology for efficient large-scale optimization. We present our vision of leveraging QC to tackle key classes of problems in future mobile networks. By analyzing and identifying common features, particularly their graph-centric representation, we propose a unified strategy involving QC algorithms. Specifically, we outline a methodology for optimization using quantum annealing as well as quantum reinforcement learning. Additionally, we discuss the main challenges that QC algorithms and hardware must overcome to effectively optimize future networks.

cs.NI↗

arXiv2025

Accurate and Scalable Simulation of Cavity-Based Networks in Modular Quantum Architectures

Cavity-mediated interconnects are a promising platform for scaling modular quantum computers by enabling high-fidelity inter-chip quantum state transmission and entanglement generation. In this work, we first model the dynamics of deterministic inter-chip quantum state transfer using the Stimulated Raman Adiabatic Passage (STIRAP) protocol, analyzing fidelity loss mechanisms under experimentally achievable qubit-cavity coupling and decoherence parameters. We then extend the NetSquid simulator, typically used for simulating long-range quantum communication networks, to support cavity-based communication channels for mediating inter-chip state transfer and entanglement generation. We model cavities as amplitude damping channels parameterized by physical system characteristics; cavity decay rate k and qubit-cavity coupling strength g, and analyze the impact of intrinsic qubit decoherence factors dictated by T1 and T2 times. Our simulations accurately represent the system's dynamics in both strong and weak coupling regimes, and identify critical trade-offs between fidelity, latency, and noise factors. The proposed framework supports faithful modeling and scalable simulation of modular architectures, and provides insights into design optimization for practical quantum network implementations.

quant-ph↗

arXiv2025

On the Impact of Classical and Quantum Communication Networks Upon Modular Quantum Computing Architecture System Performance

Modular architectures are a promising approach to scaling quantum computers beyond the limits of monolithic designs. However, non-local communications between different quantum processors might significantly impact overall system performance. In this work, we investigate the role of the network infrastructure in modular quantum computing architectures, focusing on coherence loss due to communication constraints. We analyze the impact of classical network latency on quantum teleportation and identify conditions under which it becomes a bottleneck. Additionally, we study different network topologies and assess how communication resources affect the number and parallelization of inter-core communications. Finally, we conduct a full-stack evaluation of the architecture under varying communication parameters, demonstrating how these factors influence the overall system performance. The results show that classical communication does not become a bottleneck for systems exceeding one million qubits, given current technology assumptions, even with modest clock frequencies and parallel wired interconnects. Additionally, increasing quantum communication resources generally shortens execution time, although it may introduce additional communication overhead. The optimal number of quantum links between QCores depends on both the algorithm being executed and the chosen inter-core topology. Our findings offer valuable guidance for designing modular architectures, enabling scalable quantum computing.

quant-ph↗

arXiv2025

Guided Graph Compression for Quantum Graph Neural Networks

Graph Neural Networks (GNNs) are effective for processing graph-structured data but face challenges with large graphs due to high memory requirements and inefficient sparse matrix operations on GPUs. Quantum Computing (QC) offers a promising avenue to address these issues and inspires new algorithmic approaches. In particular, Quantum Graph Neural Networks (QGNNs) have been explored in recent literature. However, current quantum hardware limits the dimension of the data that can be effectively encoded. Existing approaches either simplify datasets manually or use artificial graph datasets. This work introduces the Guided Graph Compression (GGC) framework, which uses a graph autoencoder to reduce both the number of nodes and the dimensionality of node features. The compression is guided to enhance the performance of a downstream classification task, which can be applied either with a quantum or a classical classifier. The framework is evaluated on the Jet Tagging task, a classification problem of fundamental importance in high energy physics that involves distinguishing particle jets initiated by quarks from those by gluons. The GGC is compared against using the autoencoder as a standalone preprocessing step and against a baseline classical GNN classifier. Our numerical results demonstrate that GGC outperforms both alternatives, while also facilitating the testing of novel QGNN ansatzes on realistic datasets.

cs.LG↗

arXiv2025

Frequency-Dependent Power Consumption Modeling of CMOS Transmitters for WNoC Architectures

Wireless Network-on-Chip (WNoC) systems, which wirelessly interconnect the chips of a computing system, have been proposed as a complement to existing chip-to-chip wired links. However, their feasibility depends on the availability of custom-designed high-speed, tiny, ultra-efficient transceivers. This represents a challenge due to the tradeoffs between bandwidth, area, and energy efficiency that are found as frequency increases, which suggests that there is an optimal frequency region. To aid in the search for such an optimal design point, this paper presents a behavioral model that quantifies the expected power consumption of oscillators, mixers, and power amplifiers as a function of frequency. The model is built on extensive surveys of the respective sub-blocks, all based on experimental data. By putting together the models of the three sub-blocks, a comprehensive power model is obtained, which will aid in selecting the optimal operating frequency for WNoC systems.

eess.SY↗

arXiv2025

Modeling Quantum Links for the Exploration of Distributed Quantum Computing Systems

Quantum computing offers the potential to solve certain complex problems, yet, scaling monolithic processors remains a major challenge. Modular and distributed architectures are proposed to build large-scale quantum systems while bringing the security advantages of quantum communication. At present, this requires accurate and computationally efficient models of quantum links across different scales to advance system design and guide experimental prototyping. In this work, we review protocols and models for estimating latency, losses, and fidelity in quantum communication primitives relying on quantum state distribution via microwave photons. We also propose a scalable simulation framework to support the design and evaluation of future distributed quantum computing systems.

quant-ph↗

arXiv2025

An Accurate and Efficient Analytic Model of Fidelity Under Depolarizing Noise Oriented to Large Scale Quantum System Design

Fidelity is one of the most valuable and commonly used metrics for assessing the performance of quantum circuits on error-prone quantum processors. Several approaches have been proposed to estimate circuit fidelity without executing it on quantum hardware, but they often face limitations in scalability or accuracy. In this work, we present a comprehensive theoretical framework to predict the fidelity of quantum circuits under depolarizing noise. Building on theoretical results, we propose an efficient fidelity estimation algorithm based on device calibration data. The method is thoroughly validated through simulation and execution on real hardware, demonstrating improved accuracy compared to state-of-the-art alternatives, with enhancements in prediction $R^2$ ranging from 4.96\% to 213.54\%.. The proposed approach provides a scalable and practical tool for benchmarking quantum hardware, comparing quantum software techniques such as compilation methods, obtaining computation bounds for quantum systems, and guiding hardware design decisions, making it a critical resource for developing and evaluating quantum computing technologies.

quant-ph↗

arXiv2025

Compilation Techniques for Spin Qubits in a Shuttling Bus Architecture

In this work, we explore and propose several quantum circuit mapping strategies to optimize qubit shuttling in scalable quantum computing architectures based on silicon spin qubits. Our goal is to minimize phase errors introduced during shuttling operations while reducing the overall execution time of quantum circuits. We propose and evaluate five mapping algorithms using benchmarks from quantum algorithms. The Swap Return strategy emerged as the most robust solution, offering a superior balance between execution time and error minimization by considering future qubit interactions. Additionally, we assess the importance of initial qubit placement, demonstrating that an informed placement strategy can significantly enhance the performance of dynamic mapping approaches.

quant-ph↗

arXiv2024

Toward Standardized Performance Evaluation of Flow-guided Nanoscale Localization

Nanoscale devices with Terahertz (THz) communication capabilities are envisioned to be deployed within human bloodstreams. Such devices will enable fine-grained sensing-based applications for detecting early indications (i.e., biomarkers) of various health conditions, as well as actuation-based ones such as targeted drug delivery. Associating the locations of such events with the events themselves would provide an additional utility for precision diagnostics and treatment. This vision yielded a new class of in-body localization coined under the term "flow-guided nanoscale localization". Such localization can be piggybacked on THz communication for detecting body regions in which biological events were observed based on the duration of one circulation of a nanodevice in the bloodstream. From a decades-long research on objective benchmarking of "traditional" indoor localization, as well as its eventual standardization (e.g., ISO/IEC 18305:2016), we know that in early stages the reported performance results were often incomplete (e.g., targeting a subset of relevant performance metrics), carrying out benchmarking experiments in different evaluation environments and scenarios, and utilizing inconsistent performance indicators. To avoid such a "lock-in" in flow-guided localization, in this paper we propose a workflow for standardized performance evaluation of such localization. The workflow is implemented in the form of an open-source simulation framework that is able to jointly account for the mobility of the nanodevices, in-body THz communication between with on-body anchors, and energy-related and other technological constraints (e.g., pulse-based modulation) at the nanodevice level. Accounting for these constraints, the framework is able to generate the raw data that can be streamlined into different flow-guided localization solutions for generating standardized performance benchmarks.

cs.NI↗