arXiv subjects

Eduard Alarcón

Publications and source records attributed to Eduard Alarcón.

At least 37 records · Page 2Linked to original sources

arXiv2024

Enhanced Drug Delivery via Localization-Enabled Relaying in Molecular Communication Nanonetworks

Intra-body nanonetworks hold promise for advancing targeted drug delivery (TDD) systems through molecular communications (MC). In the baseline MC-TDD system, drug-loaded nanomachines (DgNs) are positioned near the infected tissues to deliver drug molecules directly. To mitigate the decline in drug delivery efficiency caused by diffusion, we propose an enhanced MC-TDD system with a relay network. This network employs a novel localization-enabled relaying mechanism, where a nano-controller broadcasts a localization signal. DgNs then measure the received signal strength against thresholds to determine their clusters relative to the infected tissue. Additionally, our study considers the effect of multiple absorbing DgNs on the channel impulse response (CIR), a factor overlooked in previous works. Our approach improves drug delivery efficiency by $17\%$ compared to the baseline system. Importantly, we find that optimizing CIR is crucial for enhancing drug delivery efficiency. These findings pave the way for further research into optimizing CIR-based relay selection, as well as investigating the impact of factors such as drug molecule lifespan, obstruction probabilities, and flow dynamics.

cs.ET↗

arXiv2024

A MAC Protocol with Time Reversal for Wireless Networks within Computing Packages

Wireless Network-on-Chip (WNoC) is a promising concept which provides a solution to overcome the scalability issues in prevailing networks-in-package for many-core processors. However, the electromagnetic propagation inside the chip package leads to energy reverberation, resulting in Inter-Symbol Interference (ISI) with high delay spreads. Time Reversal (TR) is a technique that benefits the unique time-invariant channel with rich multipath effects to focus the energy to the desired transceiver. TR mitigates both ISI and co-channel interference, hence providing parallel communications in both space and time. Thus, TR is a versatile candidate to improve the aggregate bandwidth of wireless on-chip networks provided that a Medium Access Control (MAC) is used to efficiently share the wireless medium. In this paper, we explore a simple yet resilient TR-based MAC protocol (TR-MAC) design for WNoC. We propose to manage multiple parallel transmissions with simultaneous spatial channels in the same time slot with TR precoding and focused energy detection at the transceiver. Our results show that TR-MAC can be employed in massive computing architectures with improved latency and throughput while matching with the stringent requirements of the physical layer.

cs.ET↗

arXiv2024

Characterizing the Inter-Core Qubit Traffic in Large-Scale Quantum Modular Architectures

Modular quantum processor architectures are envisioned as a promising solution for the scalability of quantum computing systems beyond the Noisy Intermediate Scale Quantum (NISQ) devices era. Based upon interconnecting tens to hundreds of quantum cores via a quantum intranet, this approach unravels the pressing limitations of densely qubit-packed monolithic processors, mainly by mitigating the requirements of qubit control and enhancing qubit isolation, and therefore enables executing large-scale algorithms on quantum computers. In order to optimize such architectures, it is crucial to analyze the quantum state transfers occurring via inter-core communication networks, referred to as inter-core qubit traffic. This would also provide insights to improve the software and hardware stack for multi-core quantum computers. To this aim, we present a pioneering characterization of the spatio-temporal inter-core qubit traffic in large-scale circuits. The programs are executed on an all-to-all connected multi-core architecture that supports up to around 1000 qubits. We characterize the qubit traffic based on multiple performance metrics to assess the computational process and the communication overhead. Based on the showcased results, we conclude on the scalability of the presented algorithms, provide a set of guidelines to improve mapping quantum circuits to multi-core processors, and lay the foundations of benchmarking large-scale multi-core architectures.

quant-ph↗

arXiv2024

Circuit Partitioning for Multi-Core Quantum Architectures with Deep Reinforcement Learning

Quantum computing holds immense potential for solving classically intractable problems by leveraging the unique properties of quantum mechanics. The scalability of quantum architectures remains a significant challenge. Multi-core quantum architectures are proposed to solve the scalability problem, arising a new set of challenges in hardware, communications and compilation, among others. One of these challenges is to adapt a quantum algorithm to fit within the different cores of the quantum computer. This paper presents a novel approach for circuit partitioning using Deep Reinforcement Learning, contributing to the advancement of both quantum computing and graph partitioning. This work is the first step in integrating Deep Reinforcement Learning techniques into Quantum Circuit Mapping, opening the door to a new paradigm of solutions to such problems.

quant-ph↗

arXiv2024

Route-Forcing: Scalable Quantum Circuit Mapping for Scalable Quantum Computing Architectures

Quantum computers are expected to scale in size to close the gap that currently exists between quantum algorithms and quantum hardware. To this end, quantum compilation techniques must scale along with the hardware constraints, shifting the current paradigm of obtaining an optimal compilation to relying on heuristics that allow for a fast solution, even though the quality of such a solution may not be optimal. Significant concerns arise as the execution time of current mapping techniques experiences a notable increase when applied to quantum computers with a high number of qubits. In this work, we present Route-Forcing, a quantum circuit mapping algorithm that shows an average speedup of $3.7\times$ compared to the state-of-the-art scalable techniques, reducing the depth of the mapped circuit by $4.7 \times$ at the expense of adding $1.3 \times$ more SWAP gates. Moreover, the proposed mapping algorithm is adapted and tuned for what is expected to be the next generation of quantum computers, in which different processors are interconnected to increase the total number of qubits, allowing for more complex computations.

quant-ph↗

arXiv2024

Time Reversal for Near-Field Communications on Multi-chip Wireless Networks

Wireless Network-on-Chip (WNoC) has been proposed as a low-latency, versatile, and broadcast-capable complement to current interconnects in the quest for satisfying the ever-increasing communications needs of modern computing systems. However, to realize the promise of WNoC, multiple wireless links operating at several tens of Gb/s need to be created within a computing package. Unfortunately, the highly integrated and enclosed nature of such computing packages incurs significant Co-Channel Interference (CCI) and Inter-Symbol Interference (ISI), not only preventing the deployment of multiple spatial channels, but also severely limiting the symbol rate of each individual channel. In this work, Time Reversal (TR) is proposed as a means to compensate the channel impairments and enable multiple concurrent high-speed links at the chip scale. We offer evidence, via full-wave simulations at 140 GHz, that TR can increase the symbol rate by an order of magnitude and allow the deployment of multiple concurrent links towards achieving aggregate speeds in excess of 100 Gb/s. Finally, the challenges relative to the realization of TR at the chip scale are analyzed from the implementation, protocol support, and architectural perspectives.

cs.AR↗

arXiv2024

Revisiting the Mapping of Quantum Circuits: Entering the Multi-Core Era

Quantum computing represents a paradigm shift in computation, offering the potential to solve complex problems intractable for classical computers. Although current quantum processors already consist of a few hundred of qubits, their scalability remains a significant challenge. Modular quantum computing architectures have emerged as a promising approach to scale up quantum computing systems. This paper delves into the critical aspects of distributed multi-core quantum computing, focusing on quantum circuit mapping, a fundamental task to successfully execute quantum algorithms across cores while minimizing inter-core communications. We derive the theoretical bounds on the number of non-local communications needed for random quantum circuits and introduce the Hungarian Qubit Assignment (HQA) algorithm, a multi-core mapping algorithm designed to optimize qubit assignments to cores with the aim of reducing inter-core communications. Our exhaustive evaluation of HQA against state-of-the-art circuit mapping algorithms for modular architectures reveals a $4.9\times$ and $1.6\times$ improvement in terms of execution time and non-local communications, respectively, compared to the best performing algorithm. HQA emerges as a very promising scalable approach for mapping quantum circuits into multi-core architectures, positioning it as a valuable tool for harnessing the potential of quantum computing at scale.

quant-ph↗

arXiv2023

Topological Graph Signal Compression

Recently emerged Topological Deep Learning (TDL) methods aim to extend current Graph Neural Networks (GNN) by naturally processing higher-order interactions, going beyond the pairwise relations and local neighborhoods defined by graph representations. In this paper we propose a novel TDL-based method for compressing signals over graphs, consisting in two main steps: first, disjoint sets of higher-order structures are inferred based on the original signal --by clustering $N$ datapoints into $K\ll N$ collections; then, a topological-inspired message passing gets a compressed representation of the signal within those multi-element sets. Our results show that our framework improves both standard GNN and feed-forward architectures in compressing temporal link-based signals from two real-word Internet Service Provider Networks' datasets --from $30\%$ up to $90\%$ better reconstruction errors across all evaluation scenarios--, suggesting that it better captures and exploits spatial and temporal correlations over the whole graph-based network structure.

cs.LG↗

arXiv2023

Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures

Modular quantum computing architectures offer a promising alternative to monolithic designs for overcoming the scaling limitations of current quantum computers. To achieve scalability beyond small prototypes, quantum architectures are expected to adopt a modular approach, featuring clusters of tightly connected quantum bits with sparser connections between these clusters. Efficiently distributing qubits across multiple processing cores is critical for improving quantum computing systems' performance and scalability. To address this challenge, we propose the Hungarian Qubit Assignment (HQA) algorithm, which leverages the Hungarian algorithm to improve qubit-to-core assignment. The HQA algorithm considers the interactions between qubits over the entire circuit, enabling fine-grained partitioning and enhanced qubit utilization. We compare the HQA algorithm with state-of-the-art alternatives through comprehensive experiments using both real-world quantum algorithms and random quantum circuits. The results demonstrate the superiority of our proposed approach, outperforming existing methods, with an average improvement of 1.28$\times$.

quant-ph↗

arXiv2023

Interconnect Fabrics for Multi-Core Quantum Processors: A Context Analysis

Quantum computing has revolutionized the field of computer science with its extraordinary ability to handle classically intractable problems. To realize its potential, however, quantum computers need to scale to millions of qubits, a feat that will require addressing fascinating yet extremely challenging interconnection problems. In this paper, we provide a context analysis of the nascent quantum computing field from the perspective of communications, with the aim of encouraging the on-chip networks community to contribute and pave the way for truly scalable quantum computers in the decades to come.

quant-ph↗

arXiv2023

Collective Communication Patterns Using Time-Reversal Terahertz Links at the Chip Scale

Wireless communications in the terahertz band have been recently proposed as complement to conventional wired interconnects within computing packages. Such environments are typically highly reverberant, hence showing long channel impulse responses and severely limiting the achievable rates. Fortunately, this communications scenario is static and can be pre-characterized, which opens the door to techniques such as time reversal. Time reversal acts a spatial matched filter and has a spatiotemporal focusing effect, which allows not only to increase the achievable symbol rates, but also to create multiple spatial channels. In this paper, the multi-user capability of time reversal is explored in the context of wireless communications in the terahertz band within a computing package. Full-wave simulations are carried out to validate the approach, whereas modulation streams are simulated to evaluate the error rate as a function of the transmitted power, symbol rate, and number of simultaneous transmissions.

cs.AR↗

arXiv2023

Exploration of Time Reversal for Wireless Communications within Computing Packages

Wireless Network-on-Chip (WNoC) is a promising paradigm to overcome the versatility and scalability issues of conventional on-chip networks for current processor chips. However, the chip environment suffers from delay spread which leads to intense Inter-Symbol Interference (ISI). This degrades the signal when transmitting and makes it difficult to achieve the desired Bit Error Rate (BER) in this constraint-driven scenario. Time reversal (TR) is a technique that uses the multipath richness of the channel to overcome the undesired effects of the delay spread. As the flip-chip channel is static and can be characterized beforehand, in this paper we propose to apply TR to the wireless in-package channel. We evaluate the effects of this technique in time and space from an electromagnetic point of view. Furthermore, we study the effectiveness of TR in modulated data communications in terms of BER as a function of transmission rate and power. Our results show not only the spatiotemporal focusing effect of TR in a chip that could lead to multiple spatial channels, but also that transmissions using TR outperform, BER-wise, non-TR transmissions it by an order of magnitude

cs.AR↗

arXiv2023

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

quant-ph↗

arXiv2023

WHYPE: A Scale-Out Architecture with Wireless Over-the-Air Majority for Scalable In-memory Hyperdimensional Computing

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using long random vectors known as hypervectors. Among different hardware platforms capable of executing HDC algorithms, in-memory computing (IMC) has shown promise as it is very efficient in performing matrix-vector multiplications, which are common in the HDC algebra. Although HDC architectures based on IMC already exist, how to scale them remains a key challenge due to collective communication patterns that these architectures required and that traditional chip-scale networks were not designed for. To cope with this difficulty, we propose a scale-out HDC architecture called WHYPE, which uses wireless in-package communication technology to interconnect a large number of physically distributed IMC cores that either encode hypervectors or perform multiple similarity searches in parallel. In this context, the key enabler of WHYPE is the opportunistic use of the wireless network as a medium for over-the-air computation. WHYPE implements an optimized source coding that allows receivers to calculate the bit-wise majority of multiple hypervectors (a useful operation in HDC) being transmitted concurrently over the wireless channel. By doing so, we achieve a joint broadcast distribution and computation with a performance and efficiency unattainable with wired interconnects, which in turn enables massive parallelization of the architecture. Through evaluations at the on-chip network and complete architecture levels, we demonstrate that WHYPE can bundle and distribute hypervectors faster and more efficiently than a hypothetical wired implementation, and that it scales well to tens of receivers. We show that the average error rate of the majority computation is low, such that it has negligible impact on the accuracy of HDC classification tasks.

cs.DC↗

arXiv2023

Multi-channel Medium Access Control Protocols for Wireless Networks within Computing Packages

Wireless communications at the chip scale emerge as a interesting complement to traditional wire-based approaches thanks to their low latency, inherent broadcast nature, and capacity to bypass pin constraints. However, as current trends push towards massive and bandwidth-hungry processor architectures, there is a need for wireless chip-scale networks that exploit and share as many channels as possible. In this context, this work addresses the issue of channel sharing by exploring the design space of multi-channel Medium Access Control (MAC) protocols for chip-scale networks. Distinct channel assignment strategies for both random access and token passing are presented and evaluated under realistic traffic patterns. It is shown that, even with the improvements enabled by the multiple channels, both protocols maintain their intrinsic advantages and disadvantages.

cs.ET↗

arXiv2022

Towards Spatial Multiplexing in Wireless Networks within Computing Packages

Wireless Networks-on-Chip (WNoCs) are regarded as a disruptive alternative to conventional interconnection networks at the chip scale, yet limited by the relatively low aggregate bandwidth of such wireless networks. Hence, any method to increase the amount of concurrent channels in this scenario is of high value. In this direction, and since WNoC implies close integration of multiple antennas on a chip anyway, in this paper we present a feasibility study of compact monopole antenna arrays in a flip-chip environment at millimeter-wave and sub-terahertz frequencies. By means of a full-wave solver, we evaluate the feasibility to create, at will, concentrations of field in different spots of the chip. This way, we set the steps towards spatial multiplexing that enables concurrent multicast communications and also increases the aggregate bandwidth of the wireless network. Our results at 60 GHz show two clearly separable parallel channels that radiate simultaneously from two opposite corners of the chip, achieving a Signal-to-Interference Ratio (SIR) of around 40 dB, which proves that the channels are independent of each other even in such an enclosed environment. Further, we see potential to expand our approach to three or more concurrent channels, and to frequencies beyond 100 GHz.

cs.AR↗

arXiv2022

On the Enabling of Multi-receiver Communications with Reconfigurable Intelligent Surfaces

The reconfigurable intelligent surface is a promising technology for the manipulation and control of wireless electromagnetic signals. In particular, it has the potential to provide significant performance improvements for wireless networks. However, to do so, a proper reconfiguration of the reflection coefficients of unit cells is required, which often leads to complex and expensive devices. To amortize the cost, one may share the system resources among multiple transmitters and receivers. In this paper, we propose an efficient reconfiguration technique providing control over multiple beams independently. Compared to time-consuming optimization techniques, the proposed strategy utilizes an analytical method to configure the surface for multi-beam radiation. This method is easy to implement, effective and efficient since it only requires phase reconfiguration. We analyze the performance for indoor and outdoor scenarios, given the broadcast mode of operation. The aforesaid scenarios encompass some of the most challenging scenarios that wireless networks encounter. We show that our proposed technique provisions sufficient improvements in the observed channel capacity when the receivers are close to the surface in the indoor office environment scenario. Further, we report a considerable increase in the system throughput given the outdoor environment.

eess.SP↗

arXiv2022

Characterizing Qubit Traffic of a Quantum Intranet aiming at Modular Quantum Computers

Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects.

cs.ET↗