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Elena Blokhina

Publications and source records attributed to Elena Blokhina.

18 recordsLinked to original sources

Quantum Simulation of Si/SiGe Devices with Experimentally Calibrated Micromagnet Effects

Silicon-based spin qubits in Si/SiGe heterostructures are a leading platform for scalable quantum computing, yet bridging the gap between theoretical computer-aided design(CAD) models and experimental reality remains a significant challenge. Standard simulations often fail to capture critical physical phenomena, such as interface dipoles, parasitic charge accumulation, and the magnetic hysteresis of on-chip micromagnets. In this work, we present a comprehensive, experimentally calibrated 3D simulation pipeline for a 6-dot Si/SiGe device. We refine the semiconductor band alignment and introduce a semi-empirical classical charge screening model to accurately capture the formation of parasitic wells and their suppression of gate lever-arms. Furthermore, we apply the Jiles-Atherton model to account for the hysteresis and pre-magnetization of integrated cobalt micromagnets, successfully reproducing the experimental resonant frequencies across all six qubits. By coupling these calibrated electrostatic and magnetic profiles into a time-dependent rotating wave approximation (RWA) Hamiltonian, we reproduce experimental observables, including microwave power chevrons. This framework provides a robust foundation for predicting device behavior, evaluating microwave line losses, and optimizing future scalable spin qubit architectures prior to fabrication.

quant-ph↗

Transversal Gates and Magic State Distillation in an Optimally Synthesized Spin-Qubit Shuttling Bus

Fault-tolerant quantum computing requires not only reliable logical qubit storage, but also the ability to perform high-fidelity logical operations between error-corrected qubits at scale. While much of the existing literature focuses on optimizing syndrome extraction for a single logical qubit, the co-design of physical architectures that support both robust error correction and efficient logical computation remains an open challenge. In this work, we propose a multi-qubit spin-qubit shuttling bus architecture that addresses both requirements simultaneously. The architecture optimizes the physical qubit layout for syndrome extraction and supports transversal two-qubit logical gates between an arbitrary number of logical qubits, achieving all-to-all logical connectivity through coherent spin shuttling. We further propose an ancilla-sharing scheme that encodes multiple logical qubits within a single logical element, compressing the physical footprint of the processor and improving long-range gate fidelity. Extending the architecture from a one-dimensional bus to a two-dimensional grid of shuttling tracks reduces the inter-qubit distance, yielding consistent improvements in logical error. Finally, we apply the Quantum Reverse Mapping methodology at the logical level to optimize the layout of a \textit{15-to-1} magic state distillation circuit, demonstrating how the transversal capabilities of the proposed architecture can be leveraged for universal fault-tolerant computation. Taken together, these results establish a principled co-design framework that bridges the physical, error-correction, and logical computation layers of the quantum stack, and demonstrate that spin-qubit shuttling architectures are a viable and flexible substrate for scalable fault-tolerant quantum computation.

quant-ph↗

A quantum implementation of high-order power method for estimating geometric entanglement of pure states

Entanglement is one of the fundamental properties of a quantum state and is a crucial differentiator between classical and quantum computation. There are many ways to define entanglement and its measure, depending on the problem or application under consideration. Each of these measures may be computed or approximated by multiple methods. However, hardly any of these methods can be run on near-term quantum hardware. This work presents a quantum adaptation of the iterative high-order power method for estimating the geometric measure of entanglement of multi-qubit pure states using rank-1 tensor approximation. This method is executable on early fault-tolerant (hybrid) quantum hardware and does not depend on quantum memory. We simulate this algorithm and mitigate the effects of noise on the results of the computation using a theoretical model based on a known mitigation approach, which assumes a global depolarising noise channel.

quant-ph↗

Synthesizing an Optimal Spin Qubit Shuttling Bus Architecture for the Surface Code

As quantum computers scale toward millions of physical qubits, it becomes essential to robustly encode individual logical qubits to ensure fault tolerance under realistic noise. A high-quality foundational encoding allows future compilation techniques and heuristics to build on optimal or near-optimal layouts, improving scalability and error resilience. In this work, we synthesize a one-dimensional shuttling bus architecture for the rotated surface code, leveraging coherent spin-qubit shuttling, following a novel methodology we name Quantum Reverse Mapping. We formulate a mixed-integer optimization model that yields optimal solutions with relatively low execution time for small code distances, and propose a scalable heuristic that matches optimal results while maintaining linear computational complexity. We evaluate the synthesized architecture using architectural metrics, such as shuttling distance and cycle time, and full quantum simulations under realistic noise models, showing that the proposed design can sustain logical error rates as low as $2\times 10^{-10}$ per round at code distance 21, showcasing its feasibility for scalable quantum error correction in spin-based quantum processors.

quant-ph↗

Physics-Informed Optimisation of Conveyor Mode Spin Qubit Transport

Scalable quantum information processing in spin-based architectures necessitates the a bility to reliably shuttle quantum states across extended device regions with minimal decoherence. In this work, we present a physics-informed algorithm for optimizing electrostatic bias equences that enable conveyor-mode electron transport in silicon-based quantum dot devices. Our approach combines self-consistent Poisson and Schrodinger solvers to maintain a constant ground state energy and enable near-constant velocity shuttling, with potential applicability to both single-electron and hole transport. We validate the algorithm across three representative technologies: Fully-Depleted Silicon on Insulator (FD-SOI), Silicon Metal-Oxide-Seminconductor (SiMOS) and Silicon-Germanium Heterostracture (Si/SiGe), highlighting key limitations and material-specific effects that influence transport fidelity. Our findings underscore the impact of gate geometry, dielectric interfaces, and quantum dot size on the stability of shuttling operations, and offer pathways toward improving coherence preservation in large-scale quantum systems.

quant-ph↗

On the Impact of Classical and Quantum Communication Networks Upon Modular Quantum Computing Architecture System Performance

Modular architectures are a promising approach to scaling quantum computers beyond the limits of monolithic designs. However, non-local communications between different quantum processors might significantly impact overall system performance. In this work, we investigate the role of the network infrastructure in modular quantum computing architectures, focusing on coherence loss due to communication constraints. We analyze the impact of classical network latency on quantum teleportation and identify conditions under which it becomes a bottleneck. Additionally, we study different network topologies and assess how communication resources affect the number and parallelization of inter-core communications. Finally, we conduct a full-stack evaluation of the architecture under varying communication parameters, demonstrating how these factors influence the overall system performance. The results show that classical communication does not become a bottleneck for systems exceeding one million qubits, given current technology assumptions, even with modest clock frequencies and parallel wired interconnects. Additionally, increasing quantum communication resources generally shortens execution time, although it may introduce additional communication overhead. The optimal number of quantum links between QCores depends on both the algorithm being executed and the chosen inter-core topology. Our findings offer valuable guidance for designing modular architectures, enabling scalable quantum computing.

quant-ph↗

Compilation Techniques for Spin Qubits in a Shuttling Bus Architecture

In this work, we explore and propose several quantum circuit mapping strategies to optimize qubit shuttling in scalable quantum computing architectures based on silicon spin qubits. Our goal is to minimize phase errors introduced during shuttling operations while reducing the overall execution time of quantum circuits. We propose and evaluate five mapping algorithms using benchmarks from quantum algorithms. The Swap Return strategy emerged as the most robust solution, offering a superior balance between execution time and error minimization by considering future qubit interactions. Additionally, we assess the importance of initial qubit placement, demonstrating that an informed placement strategy can significantly enhance the performance of dynamic mapping approaches.

quant-ph↗

Common-Mode Control and Confinement Inversion of Electrostatically Defined Quantum Dots in a Commercial CMOS Process

Confining electrons or holes in quantum dots formed in the channel of industry-standard fully depleted silicon-on-insulator CMOS structures is a promising approach to scalable qubit architectures. In this article, we present our results on a calibrated model of a commercial nanostructure using the simulation tool Quantum TCAD, along with our experimental verification of all model predictions. We demonstrate here that quantum dots can be formed in the device channel by applying a combination of a common-mode voltage to the source and drain and a back gate voltage. Moreover, in this approach, the amount of quantum dots can be controlled and modified. Also, we report our results on an effective detuning of the energy levels in the quantum dots by varying the barrier gate voltages. Given the need and importance of scaling to larger numbers of qubits, we demonstrate here the feasibility of simulating and improving the design of quantum dot devices before their fabrication based on a commercial process.

cond-mat.mes-hall↗

Nanoscale single-electron box with a floating lead for quantum sensing: modelling and device characterization

We present an in-depth analysis of a single-electron box (SEB) biased through a floating node technique that is common in charge-coupled devices (CCDs). The device is analyzed and characterized in the context of single-electron charge-sensing techniques for integrated silicon quantum dots (QD). The unique aspect of our SEB design is the incorporation of a metallic floating node, strategically employed for sensing and precise injection of electrons into an electrostatically formed QD. To analyse the SEB, we propose an extended multi-orbital Anderson impurity model (MOAIM), adapted to our nanoscale SEB system, that is used to predict theoretically the behaviour of the SEB in the context of a charge-sensing application. The validation of the model and the sensing technique has been carried out on a QD fabricated in a fully depleted silicon on insulator (FDSOI) process on a 22-nm technological node. We demonstrate the MOAIM's efficacy in predicting the observed electronic behavior and elucidating the complex electron dynamics and correlations in the SEB. The results of our study reinforce the versatility and precision of the model in the realm of nanoelectronics and highlight the practical utility of the metallic floating node as a mechanism for charge injection and detection in integrated QDs. Finally, we identify the limitations of our model in capturing higher-order effects observed in our measurements and propose future outlooks to reconcile some of these discrepancies.

cond-mat.mes-hall↗

Statistical Static Timing Analysis of VLSI as the Statistics of Correlated Extremes

In this study, a path-based Statistical Static Timing Analysis (SSTA) is formulated as a problem within the statistics of correlated extremes. For extreme value statistics with correlations, a novel approach to studying such systems, when the correlations are small, is developed. The approach considers a system from the first principals, starting from the multivariable characteristic function. Analytical solutions to the problem of weakly correlated extremes are obtained in the form of corrections to the Gumbel distribution. These solutions are compared with Monte Carlo simulations. The applicability limits of the proposed solutions are studied. An algorithm to estimate the covariance matrix of a timing graph is proposed.

stat.AP↗

Gate--Level Statistical Timing Analysis: Exact Solutions, Approximations and Algorithms

In this paper, the Statistical Static Timing Analysis (SSTA) is considered within the block--based approach. The statistical model of the logic gate delay propagation is systematically studied and the exact analytical solution is obtained, which is strongly non-Gaussian. The procedure of handling such (non-Gaussian) distributions is described and the corresponding algorithm for the critical path delay is outlined. Finally, the proposed approach is tested and compared with Monte Carlo simulations.

eess.SY↗

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.

quant-ph↗

Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process

The proliferation of quantum computing technologies has fueled the race to build a practical quantum computer. The spectrum of the innovation is wide and encompasses many aspects of this technology, such as the qubit, control and detection mechanism, cryogenic electronics, and system integration. A few of those emerging technologies are poised for successful monolithic integration of cryogenic electronics with the quantum structure where the qubits reside. In this work, we present a fully integrated Quantum Processor Unit in which the quantum core is co-located with control and detection circuits on the same die in a commercial 22-nm FD-SOI process from GlobalFoundries. The system described in this work comprises a two dimensional (2D) 240 qubits array integrated with 8 detectors and 32 injectors operating at 3K and inside a two-stage Gifford-McMahon cryo-cooler. The power consumption of each detector and injector is 1mW and 0.27mW, respectively. The control sequence is programmed into an on-chip pattern generator that acts as a command and control block for all hardware in the Quantum Processor Unit. Using the aforementioned apparatus, we performed a quantum resonant tunneling experiment on two qubits inside the 2D qubit array. With supporting lab measurements, we demonstrate the feasibility of the proposed architecture in scaling-up the existing quantum core to thousands of qubits.

quant-ph↗

CMOS Quantum Computing: Toward A Quantum Computer System-on-Chip

Quantum computing is experiencing the transition from a scientific to an engineering field with the promise to revolutionize an extensive range of applications demanding high-performance computing. Many implementation approaches have been pursued for quantum computing systems, where currently the main streams can be identified based on superconducting, photonic, trapped-ion, and semiconductor qubits. Semiconductor-based quantum computing, specifically using CMOS technologies, is promising as it provides potential for the integration of qubits with their control and readout circuits on a single chip. This paves the way for the realization of a large-scale quantum computing system for solving practical problems. In this paper, we present an overview and future perspective of CMOS quantum computing, exploring developed semiconductor qubit structures, quantum gates, as well as control and readout circuits, with a focus on the promises and challenges of CMOS implementation.

quant-ph↗

Simulation Methodology for Electron Transfer in CMOS Quantum Dots

The construction of quantum computer simulators requires advanced software which can capture the most significant characteristics of the quantum behavior and quantum states of qubits in such systems. Additionally, one needs to provide valid models for the description of the interface between classical circuitry and quantum core hardware. In this study, we model electron transport in semiconductor qubits based on an advanced CMOS technology. Starting from 3D simulations, we demonstrate an order reduction and the steps necessary to obtain ordinary differential equations on probability amplitudes in a multi-particle system. We compare numerical and semi-analytical techniques concluding this paper by examining two case studies: the electron transfer through multiple quantum dots and the construction of a Hadamard gate simulated using a numerical method to solve the time-dependent Schrodinger equation and the tight-binding formalism for a time-dependent Hamiltonian.

quant-ph↗

CMOS Position-Based Charge Qubits: Theoretical Analysis of Control and Entanglement

In this study, a formal definition, robustness analysis and discussion on the control of a position-based semiconductor charge qubit are presented. Such a qubit can be realized in a chain of coupled quantum dots, forming a register of charge-coupled transistor-like devices, and is intended for CMOS implementation in scalable quantum computers. We discuss the construction and operation of this qubit, its Bloch sphere, and relation with maximally localized Wannier functions which define its position-based nature. We then demonstrate how to build a tight-binding model of single and multiple interacting qubits from first principles of the Schrödinger formalism. We provide all required formulae to calculate the maximally localized functions and the entries of the Hamiltonian matrix in the presence of interaction between qubits. We use three illustrative examples to demonstrate the electrostatic interaction of electrons and discuss how to build a model for many-electron (qubit) system. To conclude this study, we show that charge qubits can be entangled through electrostatic interaction.

cond-mat.mes-hall↗

Electrostatic Near-Limits Kinetic Energy Harvesting from Arbitrary Input Vibrations

The full architecture of an electrostatic kinetic energy harvester (KEH) based on the concept of near-limits KEH is reported. This concept refers to the conversion of kinetic energy to electric energy, from environmental vibrations of arbitrary forms, and at rates that target the physical limits set by the device's size and the input excitation characteristics. This is achieved thanks to the synthesis of particular KEH's mass dynamics, that maximize the harvested energy. Synthesizing these dynamics requires little hypotheses on the exact form of the input vibrations. In the proposed architecture, these dynamics are implemented by an adequate mechanical control which is synthesized by the electrostatic transducer. An interface circuit is proposed to carry out the necessary energy transfers between the transducer and the system's energy tank. A computation and finite-state automaton unit controls the interface circuit, based on the external input and on the system's mechanical state. The operation of the reported near-limits KEH is illustrated in simulations that demonstrate proof of concept of the proposed architecture. A figure of $68\%$ of the absolute limit of the KEH's input energy for the considered excitation is attained. This can be further improved by complete system optimization that takes into account the application constraints, the control law, the mechanical design of the transducer, the electrical interface design, and the sensing and computation blocks.

physics.app-ph↗

Properties of Coupled Single-Electron Lines

Fundamental properties of two electrostatically interacting single-electron lines (SEL) are determined from a minimalistic tight-binding model. The lines are represented by a chain of coupled quantum wells that could be implemented in a mainstream nanoscale CMOS process technology and tuned electrostatically by DC or AC voltage biases. The obtained results show an essential qualitative difference with two capacitively coupled classical electrical lines. The derived equations and their solutions prove that the two coupled SET lines can create an entanglement between electrons. The results indicate a possibility of constructing electrostatic (non-spin) coupled qubits that could be used as building blocks in a CMOS quantum computer.

cond-mat.mes-hall↗