arXiv subjects

Farzan Jazaeri

Publications and source records attributed to Farzan Jazaeri.

17 recordsLinked to original sources

arXiv2024

Simplified EPFL GaN HEMT Model

This paper introduces a simplified and design-oriented version of the EPFL HEMT model [1], focusing on the normalized transconductance-to-current characteristic (Gm/ID ). Relying on these figures, insights into GaN HEMT modeling in relation to technology offers a comprehensive understanding of the device behavior. Validation is achieved through measured transfer characteristics of GaN HEMTs fabricated at IMEC on a broad range of biases. This simplified approach should enable a simple and effective circuit design methodology with AlGaN/GaN HEMT heterostructures.

physics.app-ph↗

arXiv2023

Generalized Boltzmann relations in semiconductors including band tails

Boltzmann relations are widely used in semiconductor physics to express the charge-carrier densities as a function of the Fermi level and temperature. However, these simple exponential relations only apply to sharp band edges of the conduction and valence bands. In this article, we present a generalization of the Boltzmann relations accounting for exponential band tails. To this end, the required Fermi-Dirac integral is first recast as a Gauss hypergeometric function, followed by a suitable transformation of that special function, and a zeroth-order series expansion using the hypergeometric series. This results in simple relations for the electron and hole densities that each involve two exponentials. One exponential depends on the temperature and the other one on the band-tail parameter. The proposed relations tend to the Boltzmann relations if the band-tail parameters tend to zero. This work comes timely for the modeling of classical semiconductor devices at cryogenic temperatures for large-scale quantum computing.

physics.app-ph↗

arXiv2023

Inflection Phenomenon in Cryogenic MOSFET Behavior

This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the current in weak and moderate inversion at a given gate voltage compared to the drift-diffusion current. This phenomenon is explained by introducing a Gaussian distribution of localized states centered around the band edge. The localized states are attributed to disorder and interface traps. The proposed model allows to extract the density of localized states at the interface from the dc current measurements.

cond-mat.mes-hall↗

arXiv2021

Non-Hysteretic Condition in Negative Capacitance Junctionless FETs

This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77K to 400K. This approach has been assessed with numerical TCAD simulations.

physics.app-ph↗

arXiv2020

Negative Capacitance DG Junctionless FETs: A Charge-based Modeling Investigation of Swing, Overdrive and Short Channel Effect

In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, for the first time, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels (0.1 {\textmu}A/{\textmu}m). Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

physics.app-ph↗

arXiv2020

Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs

This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the first-order perturbation theory for calculating eigenstates and corresponding wave functions obtained by the Schrodinger equation in the cylindrical coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step toward the analysis of circuits mainly biosensors based on junctionless nanowire transistors.

physics.app-ph↗

arXiv2019

Revised theoretical limit of subthreshold swing in field-effect transistors

This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures. Below a critical temperature, the derived limit saturates to a value that is independent of temperature and proportional to the extent of a band tail. Since the saturation is universally observed in different types of MOSFETs (regardless of dimension or semiconductor material), the band tail is attributed to the finite periodicity of the lattice in a semiconductor volume, and to a lesser extent to additional lattice perturbations such as defects or disorder.

cond-mat.mes-hall↗

arXiv2019

Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.

physics.app-ph↗

arXiv2019

A Review on Quantum Computing: Qubits, Cryogenic Electronics and Cryogenic MOSFET Physics

Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is currently way ahead of all other qubit implementations. This paper briefly reviews the progress made on the silicon-based QC platform, which is highly promising to meet the scale-up challenges by leveraging the semiconductor industry. We look at different types of qubits, the advantages of silicon, and techniques for qubit manipulation in the solid state. Finally, we discuss the possibility of co-integrating silicon qubits with FET-based, cooled front-end electronics, and review the device physics of MOSFETs at deep cryogenic temperatures.

quant-ph↗

arXiv2019

An Explicit Model for Ultra-thin Gate-All-Around Junctionless Nanowire FETs, Including 2D Quantum Confinement

In this paper, we develop an explicit model to predict the DC electrical behavior in ultra-thin surrounding gate junctionless nanowire FET. The proposed model takes into account 2D electrical and geometrical confinements of carrier charge density within few discrete sub-bands. Combining a parabolic approximation of the Poisson equation, first order perturbation theory for the Schrodinger subband energy eigenvalues, and Fermi-Dirac statistics for the confined carrier density leads to an explicit solution of the DC characteristic in ultra-thin junctionless devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on junctionless nanowire devices.

physics.app-ph↗

arXiv2019

Cryogenic MOSFET Threshold Voltage Model

This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poisson's equation including bandgap widening, intrinsic carrier-density scaling, and incomplete ionization. We demonstrate that accounting for incomplete ionization in the expression of the threshold voltage is critical for an accurate estimation of the current. The model is validated with our experimental results from nMOSFETs of a 28-nm CMOS process. The developed model is a key element for a cryo-CMOS compact model and can serve as a guide to optimize processes for high-performance cryo-computing and ultra-low-power quantum computing.

physics.app-ph↗

arXiv2018

Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2\,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4\,K and 4.2\,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77\,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

cond-mat.mes-hall↗

arXiv2018

Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing

In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo- CMOS circuits implemented in a 28 nm FDSOI technology.

physics.app-ph↗

arXiv2018

Charge-Based Model for Ultrathin Junctionless DG FETs, Including Quantum Confinement

This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction to the infinite quantum well. When restricting the analysis to the first and second quantized states, the free carrier charge distribution and the current in an ultrathin body JLDG FETs are in agreement with numerical TCAD simulations in all the regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

physics.app-ph↗

arXiv2018

Cryogenic MOS Transistor Model

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to zero Kelvin as a result of dopant freeze-out in cryogenic equilibrium. Explicit MOS transistor expressions are then derived including incomplete dopant-ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependency of the interface-trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on a commercially available 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically-accurate compact models dedicated to low-temperature CMOS circuit simulation.

cond-mat.mes-hall↗

arXiv2018

Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing

This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems.

cond-mat.mes-hall↗

arXiv2018

Negative Capacitance as Digital and Analog Performance Booster for Complementary MOS Transistors

Boltzmann tyranny poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMOS technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. Recent demonstrations of negative capacitance concerned mainly n-type MOSFETs and their subthreshold slope. An effective technology booster should be capable of improving the performance of both n- and p-type transistors. In this work, we report a significant enhancement in both digital (subthreshold swing, on-current over off-current ratio, and overdrive) and analog (transconductance and current efficiency factor) FoM of commercial 28nm CMOS process by exploiting a PZT capacitor as the negative capacitance booster. Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 10$^5$ V$^{-1}$ is obtained in both n- and p-type MOSFETs at room temperature. The overdrive voltage is enhanced up to 0.45 V, leading to a supply voltage reduction of 50\%.

physics.app-ph↗