arXiv subjects

Francesca Iacopi

Publications and source records attributed to Francesca Iacopi.

5 recordsLinked to original sources

arXiv2026

Seed Layer Engineering for Effective Charge Transfer Doping of MoS$_2$ Transistors

Integrating two-dimensional semiconductors such as MoS$_2$ with dielectric materials remains a central challenge for their use in future logic technologies. While seed layers are typically introduced to promote dielectric nucleation and adhesion, we show that they also critically govern charge-transfer doping and, in turn, transistor performance. Back-gated monolayer MoS$_2$ transistors passivated on their top-surface with a Ta-seed/HfO$_x$ dielectric stack were fabricated and characterized electrically and physically using Raman, photoluminescence, and X-ray photoelectron spectroscopies. Threshold voltage and on-current varied strongly with Ta-seed thickness and deposition conditions, and these changes correlated with signatures observed across all spectroscopic probes. The results reveal that the seed layer both introduces disorder into the MoS$_2$ channel and modifies the interfacial charge environment controlling charge transfer between HfO$_x$ and MoS$_2$. Optical spectroscopy shows that on-current tracks seed-induced disorder, whereas X-ray photoelectron spectroscopy indicates that threshold voltage correlates with shifts in the local electrostatic environment associated with interfacial charge transfer. Better performance was obtained with ultrathin 0.2 nm Ta seed layers deposited under oxygen-poor conditions, which limit deposition-induced damage while facilitating charge transfer. These findings identify seed-layer engineering as a key strategy for controlling disorder and interfacial doping in MoS$_2$ devices and establish multimodal spectroscopy as a practical during-fabrication approach for process development and monitoring.

cond-mat.mtrl-sci↗

arXiv2025

LIMO: Low-Power In-Memory-Annealer and Matrix-Multiplication Primitive for Edge Computing

Combinatorial optimization (CO) underpins applications in science and engineering, ranging from logistics to electronic design automation. A classic example is the NP-complete Traveling Salesman Problem (TSP). Finding exact solutions for large-scale TSP instances remains computationally intractable; on von Neumann architectures, such solvers are constrained by the memory wall, incurring compute-memory traffic that grows with instance size. Metaheuristics, such as simulated annealing implemented on compute-in-memory (CiM) architectures, offer a way to mitigate the von Neumann bottleneck. This is accomplished by performing in-memory optimization cycles to rapidly find approximate solutions for TSP instances. Yet this approach suffers from degrading solution quality as instance size increases, owing to inefficient state-space exploration. To address this, we present LIMO, a mixed-signal computational macro that implements an in-memory annealing algorithm with reduced search-space complexity. The annealing process is aided by the stochastic switching of spin-transfer-torque magnetic-tunnel-junctions (STT-MTJs) to escape local minima. For large instances, our macro co-design is complemented by a refinement-based divide-and-conquer algorithm amenable to parallel optimization in a spatial architecture. Consequently, our system comprising several LIMO macros achieves superior solution quality and faster time-to-solution on instances up to 85,900 cities compared to prior hardware annealers. The modularity of our annealing peripherals allows the LIMO macro to be reused for other applications, such as vector-matrix multiplications (VMMs). This enables our architecture to support neural network inference. As an illustration, we show image classification and face detection with software-comparable accuracy, while achieving lower latency and energy consumption than baseline CiM architectures.

cs.ET↗

arXiv2025

TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering

Ising solvers with hierarchical clustering have shown promise for large-scale Traveling Salesman Problems (TSPs), in terms of latency and energy. However, most of these methods still face unacceptable quality degradation as the problem size increases beyond a certain extent. Additionally, their hardware-agnostic adoptions limit their ability to fully exploit available hardware resources. In this work, we introduce TAXI -- an in-memory computing-based TSP accelerator with crossbar(Xbar)-based Ising macros. Each macro independently solves a TSP sub-problem, obtained by hierarchical clustering, without the need for any off-macro data movement, leading to massive parallelism. Within the macro, Spin-Orbit-Torque (SOT) devices serve as compact energy-efficient random number generators enabling rapid "natural annealing". By leveraging hardware-algorithm co-design, TAXI offers improvements in solution quality, speed, and energy-efficiency on TSPs up to 85,900 cities (the largest TSPLIB instance). TAXI produces solutions that are only 22% and 20% longer than the Concorde solver's exact solution on 33,810 and 85,900 city TSPs, respectively. TAXI outperforms a current state-of-the-art clustering-based Ising solver, being 8x faster on average across 20 benchmark problems from TSPLib.

cs.ET↗

arXiv2020

Engineering the dissipation of crystalline micromechanical resonators

High quality micro- and nano-mechanical resonators are widely used in sensing, communications and timing, and have future applications in quantum technologies and fundamental studies of quantum physics. Crystalline thin-films are particularly attractive for such resonators due to their prospects for high quality, intrinsic stress and yield strength, and low dissipation. However, when grown on a silicon substrate, interfacial defects arising from lattice mismatch with the substrate have been postulated to introduce additional dissipation. Here, we develop a new backside etching process for single crystal silicon carbide microresonators that allows us to quantitatively verify this prediction. By engineering the geometry of the resonators and removing the defective interfacial layer, we achieve quality factors exceeding a million in silicon carbide trampoline resonators at room temperature, a factor of five higher than without the removal of the interfacial defect layer. We predict that similar devices fabricated from ultrahigh purity silicon carbide and leveraging its high yield strength, could enable room temperature quality factors as high as $6\times10^9$

physics.app-ph↗

arXiv2016

Graphene as a p-type metal for ultimate miniaturization

We report macroscopic sheets of highly conductive bilayer graphene with exceptionally high hole concentrations of ~ $10^{15}$ $cm^{-2}$ and unprecedented sheet resistances of 20-25 Ω per square over macroscopic scales, and obtained in-situ over a thin cushion of molecular oxygen on a silicon substrate. The electric and electronic properties of this specific configuration remain stable upon thermal anneals and months of exposure to air. We further report a complementary ab-initio study, predicting an enhancement of graphene adhesion energy of up to a factor 20, also supported by experimental fracture tests. Our results show that the remarkable properties of graphene can be realized in a reliable fashion using a high-throughput process. In addition to providing exceptional material properties, the growth process we employed is scalable to large areas so that the outstanding conduction properties of graphene can be harnessed in devices fabricated via conventional semiconductor manufacturing processes. We anticipate that the approach will provide the necessary scalability and reliability for future developments in the graphene nanoscience and technology fields, especially in areas where further miniaturization is hampered by size effects and electrical reliability of classical conductors.

cond-mat.mtrl-sci↗