arXiv subjects

G. Iacobucci

Publications and source records attributed to G. Iacobucci.

At least 19 recordsLinked to original sources

arXiv2024

Testbeam Characterization of a SiGe BiCMOS Monolithic Silicon Pixel Detector with Internal Gain Layer

A monolithic silicon pixel ASIC prototype, produced in 2024 as part of the Horizon 2020 MONOLITH ERC Advanced project, was tested with a 120 GeV/c pion beam. The ASIC features a matrix of hexagonal pixels with a 100 μm pitch, read by low-noise, high-speed front-end electronics built using 130 nm SiGe BiCMOS technology. It includes the PicoAD sensor, which employs a continuous, deep PN junction to generate avalanche gain. Data were taken across power densities from 0.05 to 2.6 W/cm2 and sensor bias voltages from 90 to 180 V. At the highest bias voltage, corresponding to an electron gain of 50, and maximum power density, an efficiency of (99.99 \pm 0.01)% was achieved. The time resolution at this working point was (24.3 \pm 0.2) ps before time-walk correction, improving to (12.1 \pm 0.3) ps after correction.

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arXiv2024

Testbeam results of irradiated SiGe BiCMOS monolithic silicon pixel detector without internal gain layer

Samples of the monolithic silicon pixel ASIC prototype produced in 2022 within the framework of the Horizon 2020 MONOLITH ERC Advanced project were irradiated with 70 MeV protons up to a fluence of 1 x 1016 neq/cm2, and then tested using a beam of 120 GeV/c pions. The ASIC contains a matrix of 100 μm pitch hexagonal pixels, readout out by low noise and very fast frontend electronics produced in a 130 nm SiGe BiCMOS technology process. The dependence on the proton fluence of the efficiency and the time resolution of this prototype was measured with the frontend electronics operated at a power density between 0.13 and 0.9 W/cm2. The testbeam data show that the detection efficiency of 99.96% measured at sensor bias voltage of 200 V before irradiation becomes 96.2% after a fluence of 1 x 1016 neq/cm2. An increase of the sensor bias voltage to 300 V provides an efficiency to 99.7% at that proton fluence. The timing resolution of 20 ps measured before irradiation rises for a proton fluence of 1 x 1016 neq/cm2 to 53 and 45 ps at HV = 200 and 300 V, respectively.

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arXiv2024

Time Resolution of a SiGe BiCMOS Monolithic Silicon Pixel Detector without Internal Gain Layer with a Femtosecond Laser

The time resolution of the second monolithic silicon pixel prototype produced for the MONOLITH H2020 ERC Advanced project was studied using a femtosecond laser. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Silicon wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. At the highest frontend power density tested of 2.7 W/cm2, the time resolution with the femtosecond laser pulses was found to be 45 ps for signals generated by 1200 electrons, and 3 ps in the case of 11k electrons, which corresponds approximately to 0.4 and 3.5 times the most probable value of the charge generated by a minimum-ionizing particle. The results were compared with testbeam data taken with the same prototype to evaluate the time jitter produced by the fluctuations of the charge collection.

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arXiv2023

Radiation Tolerance of SiGe BiCMOS Monolithic Silicon Pixel Detectors without Internal Gain Layer

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 x 10^16 1 MeV n_eq/cm^2. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6 x 10^14 n_eq /cm^2 . The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35 {^\circ}C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm^2, the time jitter of the most-probable signal amplitude was estimated to be 21 ps for proton fluence up to 6 x 10 n_eq/cm^2 and 57 ps at 1 x 10^16 n_eq/cm^2 . Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 x 10^16 n_eq/cm^2.

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arXiv2023

20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer

A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer of 350 Ωcm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.

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arXiv2022

Picosecond Avalanche Detector -- working principle and gain measurement with a proof-of-concept prototype

The Picosecond Avalanche Detector is a multi-junction silicon pixel detector based on a $\mathrm{(NP)_{drift}(NP)_{gain}}$ structure, devised to enable charged-particle tracking with high spatial resolution and picosecond time-stamp capability. It uses a continuous junction deep inside the sensor volume to amplify the primary charge produced by ionizing radiation in a thin absorption layer. The signal is then induced by the secondary charges moving inside a thicker drift region. A proof-of-concept monolithic prototype, consisting of a matrix of hexagonal pixels with 100 $μ$m pitch, has been produced using the 130 nm SiGe BiCMOS process by IHP microelectronics. Measurements on probe station and with a $^{55}$Fe X-ray source show that the prototype is functional and displays avalanche gain up to a maximum electron gain of 23. A study of the avalanche characteristics, corroborated by TCAD simulations, indicates that space-charge effects due to the large primary charge produced by the conversion of X-rays from the $^{55}$Fe source limits the effective gain.

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arXiv2022

Testbeam Results of the Picosecond Avalanche Detector Proof-Of-Concept Prototype

The proof-of-concept prototype of the Picosecond Avalanche Detector, a multi-PN junction monolithic silicon detector with continuous gain layer deep in the sensor depleted region, was tested with a beam of 180 GeV pions at the CERN SPS. The prototype features low noise and fast SiGe BiCMOS frontend electronics and hexagonal pixels with 100 μm pitch. At a sensor bias voltage of 125 V, the detector provides full efficiency and average time resolution of 30, 25 and 17 ps in the overall pixel area for a power consumption of 0.4, 0.9 and 2.7 W/cm^2, respectively. In this first prototype the time resolution depends significantly on the distance from the center of the pixel, varying at the highest power consumption measured between 13 ps at the center of the pixel and 25 ps in the inter-pixel region.

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arXiv2022

Efficiency and time resolution of monolithic silicon pixel detectors in SiGe BiCMOS technology

A monolithic silicon pixel detector prototype has been produced in the SiGe BiCMOS SG13G2 130 nm node technology by IHP. The ASIC contains a matrix of hexagonal pixels with pitch of approximately 100 $μ$m. Three analog pixels were calibrated in laboratory with radioactive sources and tested in a 180 GeV/c pion beamline at the CERN SPS. A detection efficiency of $\left(99.9^{+0.1}_{-0.2}\right)$% was measured together with a time resolution of $(36.4 \pm 0.8)$ps at the highest preamplifier bias current working point of 150 $μ$A and at a sensor bias voltage of 160 V. The ASIC was also characterized at lower bias voltage and preamplifier current.

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arXiv2020

Time resolution and power consumption of a monolithic silicon pixel prototype in SiGe BiCMOS technology

SiGe BiCMOS technology can be used to produce ultra-fast, low-power silicon pixel sensors that provide state-of-the-art time resolution even without an internal gain mechanism. The development of such sensors requires the identification of the main factors that may degrade the timing performance and the characterisation of the dependance of the sensor time resolution on the amplifier power consumption. Measurements with a $ \mathrm{^{90}Sr} $ source of a prototype sensor produced in SG13G2 technology from IHP Microelectronics, shows a time resolution of 140 ps at an amplifier current of 7 $ \mathrmμ $A and 45 ps at higher power consumption. A full simulation shows that the resolution on the measurement of the signal time-over-threshold, used to correct for time walk, is the main factor affecting the timing performance.

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arXiv2020

Electrical Characterization of 180 nm ATLASPix2 HV-CMOS Monolithic Prototypes for the High-Luminosity LHC

We report on the experimental study made on a successive prototype of High-Voltage CMOS (HV-CMOS) ATLASPix2 sensor for the tracking detector application, developed with 180 nm feature size. These sensors are to qualify mainly the peripheral data processing blocks (e.g. Command Decoder, Trigger Buffer, etc.). It is a smaller version of 24 X 36 pixelated sensor in comparison to the earlier generation of ATLASPix1 fabricated in both ams AG, Austria, and TSI Semiconductors, USA. While ams produced ATLASPix2 showed breakdown voltage 50 V in nonirradiated condition as it was seen on its predecessors ATLASpix1, TSI produced prototypes reported breakdown voltage greater than 100 V. The chosen wafer of MCz 20 Ohm.cm P-type substrate resistivity can deplete a few tenths of um, where the process-driven surface damage can have a greater impact on device operating conditions before and after irradiation. In an aim to understand device intrinsic performance at the irradiated case, a dedicated neutron irradiation campaign has been made at JSI for different fluences. Characterizations have been performed at different temperatures after irradiation to analyze the leakage current and breakdown voltage before and after irradiation. TSI prototypes showed a breakdown voltage decrease 90 V due to impact ionization and enhanced effective doping concentration. Results demonstrated for the neutron-irradiated devices up to the fluence of 2 X 10^15 neq/cm2 can still safely be operated at a voltage high enough to allow for high efficiency. Accelerated Annealing steps also made on selective irradiated ATLASPix2 samples, equivalent to more than two years of room-temperature annealing (at 20 degC), and they showed the reassuring expected breakdown voltage increase and damage constant rate alpha^* (geometry dependent) decrease, driven by the beneficial annealing.

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arXiv2020

MuPix and ATLASPix -- Architectures and Results

High Voltage Monolithic Active Pixel Sensors (HV-MAPS) are based on a commercial High Voltage CMOS process and collect charge by drift inside a reversely biased diode. HV-MAPS represent a promising technology for future pixel tracking detectors. Two recent developments are presented. The MuPix has a continuous readout and is being developed for the Mu3e experiment whereas the ATLASPix is being developed for LHC applications with a triggered readout. Both variants have a fully monolithic design including state machines, clock circuitries and serial drivers. Several prototypes and design variants were characterised in the lab and in testbeam campaigns to measure efficiencies, noise, time resolution and radiation tolerance. Results from recent MuPix and ATLASPix prototypes are presented and prospects for future improvements are discussed.

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arXiv2019

A 50 ps resolution monolithic active pixel sensor without internal gain in SiGe BiCMOS technology

A monolithic pixelated silicon detector designed for high time resolution has been produced in the SG13G2 130 nm SiGe BiCMOS technology of IHP Mikroelektronik. This proof-of-concept chip contains hexagonal pixels of 65 μm and 130 μm side. The SiGe front-end electronics implemented provides an equivalent noise charge of 90 and 160 electrons for a pixel capacitance of 70 and 220 fF, respectively, and a total time walk of less than 1 ns. Lab measurements with a 90Sr source show a time resolution of the order of 50 ps. This result is competitive with silicon technologies that integrate an avalanche gain mechanism.

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arXiv2019

Characterisation of AMS H35 HV-CMOS monolithic active pixel sensor prototypes for HEP applications

Monolithic active pixel sensors produced in High Voltage CMOS (HV-CMOS) technology are being considered for High Energy Physics applications due to the ease of production and the reduced costs. Such technology is especially appealing when large areas to be covered and material budget are concerned. This is the case of the outermost pixel layers of the future ATLAS tracking detector for the HL-LHC. For experiments at hadron colliders, radiation hardness is a key requirement which is not fulfilled by standard CMOS sensor designs that collect charge by diffusion. This issue has been addressed by depleted active pixel sensors in which electronics are embedded into a large deep implantation ensuring uniform charge collection by drift. Very first small prototypes of hybrid depleted active pixel sensors have already shown a radiation hardness compatible with the ATLAS requirements. Nevertheless, to compete with the present hybrid solutions a further reduction in costs achievable by a fully monolithic design is desirable. The H35DEMO is a large electrode full reticle demonstrator chip produced in AMS 350 nm HV-CMOS technology by the collaboration of Karlsruher Institut für Technologie (KIT), Institut de Física d'Altes Energies (IFAE), University of Liverpool and University of Geneva. It includes two large monolithic pixel matrices which can be operated standalone. One of these two matrices has been characterised at beam test before and after irradiation with protons and neutrons. Results demonstrated the feasibility of producing radiation hard large area fully monolithic pixel sensors in HV-CMOS technology. H35DEMO chips with a substrate resistivity of 200$Ω$ cm irradiated with neutrons showed a radiation hardness up to a fluence of $10^{15}$n$_{eq}$cm$^{-2}$ with a hit efficiency of about 99% and a noise occupancy lower than $10^{-6}$ hits in a LHC bunch crossing of 25ns at 150V.

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arXiv2018

The TT-PET Data Acquisition and Trigger System

This paper describes the data acquisition and trigger system of the Thin Time-of-flight PET (TT-PET) scanner. The system is designed to read out in the order of 1000 pixel sensors used in the scanner and to provide a reference timing signal to each sensor in order to measure time differences of better than 30 ps. This clock distribution is measured to have a jitter of less than 4 ps at the sensors. Collected data is locally processed before being forwarded to storage. Data flow as well as control, configuration and monitoring aspects are are also addressed.

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arXiv2018

Test beam measurement of ams H35 HV-CMOS capacitively coupled pixel sensor prototypes with high-resistivity substrate

In the context of the studies of the ATLAS High Luminosity LHC programme, radiation tolerant pixel detectors in CMOS technologies are investigated. To evaluate the effects of substrate resistivity on CMOS sensor performance, the H35DEMO demonstrator, containing different diode and amplifier designs, was produced in ams H35 HV-CMOS technology using four different substrate resistivities spanning from $\mathrm{80}$ to $\mathrm{1000~Ω\cdot cm}$. A glueing process using a high-precision flip-chip machine was developed in order to capacitively couple the sensors to FE-I4 Readout ASIC using a thin layer of epoxy glue with good uniformity over a large surface. The resulting assemblies were measured in beam test at the Fermilab Test Beam Facilities with 120 GeV protons and CERN SPS H8 beamline using 80 GeV pions. The in-time efficiency and tracking properties measured for the different sensor types are shown to be compatible with the ATLAS ITk requirements for its pixel sensors.

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arXiv2018

Test beam measurement of the first prototype of the fast silicon pixel monolithic detector for the TT-PET project

The TT-PET collaboration is developing a PET scanner for small animals with 30 ps time-of-flight resolution and sub-millimetre 3D detection granularity. The sensitive element of the scanner is a monolithic silicon pixel detector based on state-of-the-art SiGe BiCMOS technology. The first ASIC prototype for the TT-PET was produced and tested in the laboratory and with minimum ionizing particles. The electronics exhibit an equivalent noise charge below 600 e- RMS and a pulse rise time of less than 2 ns, in accordance with the simulations. The pixels with a capacitance of 0.8 pF were measured to have a detection efficiency greater than 99% and, although in the absence of the post-processing, a time resolution of approximately 200 ps.

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arXiv2017

Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\cdot 10^{14}$ and $5\cdot 10^{15}$ 1-MeV-n$_\textrm{eq}$/cm$^2$. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of $85\,$V. The sample irradiated to a fluence of $1\cdot 10^{15}$ n$_\textrm{eq}$/cm$^2$ - a relevant value for a large volume of the upgraded tracker - exhibited 99.7% average hit efficiency. The results give strong evidence for the radiation tolerance of HV-CMOS sensors and their suitability as sensors for the experimental HL-LHC upgrades and future large-area silicon-based tracking detectors in high-radiation environments.

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arXiv2016

Development of a modular test system for the silicon sensor R&D of the ATLAS Upgrade

High Voltage CMOS sensors are a promising technology for tracking detectors in collider experiments. Extensive R&D studies are being carried out by the ATLAS Collaboration for a possible use of HV-CMOS in the High Luminosity LHC upgrade of the Inner Tracker detector. CaRIBOu (Control and Readout Itk BOard) is a modular test system developed to test Silicon based detectors. It currently includes five custom designed boards, a Xilinx ZC706 development board, FELIX (Front-End LInk eXchange) PCIe card and a host computer. A software program has been developed in Python to control the CaRIBOu hardware. CaRIBOu has been used in the testbeam of the HV-CMOS sensor CCPDv4 at CERN. Preliminary results have shown that the test system is very versatile. Further development is ongoing to adapt to different sensors, and to make it available to various lab test stands.

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